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UART Data Transfer Modes
If DMA is enabled, the DMA engine always writes the data into the
UART_THR
register, and the written word is
transmitted with the appending address bit set low.
The polarity of transmit data is selectable, using the UART_CTL.TPOLC bit.
MDB Receive Operation
Receive operations use the same data format as the transmit configuration, except that the number of stop bits is
always assumed to be 1. After detection of the start bit, the received word is shifted into the
UART_RSR
register at
the programmed bit.
Normally, the receiver samples every incoming bit at exactly the 7th, 8th and 9th sample clock. If, however, the
UART_CLK.EDBO bit is set, the receiver samples the bits roughly at 7/16th, 8/16th, and 9/16th of their period.
This configuration achieves better bit rate granularity and accuracy needed at high operation speeds. Hardware de-
sign must ensure that the incoming signal is stable between 6/16th and 10/16th of the nominal bit period.
After the appropriate number of bits (including address, parity, and stop bits) is received, the
register is
UART_RSR
transferred to the receive FIFO and accessible through the
UART_RBR
register.
The polarity of receive data is selectable, using the UART_CTL.RPOLC bit.
DMA Mode
In DMA mode, separate receive and transmit DMA channels move data between the UART and memory. The soft-
ware does not have to move data; it just has to set up the appropriate transfers either through the descriptor mecha-
nism or through autobuffer mode.
DMA channels provide a 4-deep FIFO, resulting in total buffer capabilities of 6 words at the transmit side and 9
words at the receive side. In DMA mode, the bus activity and arbitration mechanism determine the latency. The
processor loading and interrupt priorities do not determine the latency.
To enable UART DMA, first set up the system DMA control registers. Then, enable the UART_IMSK.ERBFI or
UART_IMSK.ETBEI interrupts. This sequence is necessary because these interrupt request lines double as DMA
request lines. With DMA enabled, once these requests are received, the DMA control unit generates a direct memo-
ry access. If DMA is not enabled, the UART interrupt is passed on to the system interrupt handling unit. The status
interrupt for the UART goes directly to the system event controller (SEC), bypassing the DMA unit completely.
For transmit DMA, programs must set the DMA_CFG.SYNC bit. With this bit set, interrupt generation is delayed
until the entire DMA FIFO is drained to the UART module. The UART transmit DMA interrupt service routine
can disable the DMA or to clear the UART_IMSK.ETBEI control bit only when the DMA_CFG.SYNC bit is set.
Otherwise, up to four data bytes can be lost.
When the UART_IMSK.ETBEI bit is set, an initial transmit DMA request is issued immediately. The program
then clears the UART_IMSK.ETBEI bit through the DMA service routine.
In DMA transmit mode, the UART_IMSK.ETBEI bit enables the peripheral request to the DMA FIFO. The
DMA_CFG.EN bit enables the strobe on the memory side. If the DMA count is less than the DMA FIFO depth,
which is 4, then the DMA interrupt can be requested before the UART_IMSK.ETBEI bit is set. If this behavior is
unwanted, set the DMA_CFG.SYNC bit.
17–16
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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