Analog Devices ADSP-SC58 Series Hardware Reference Manual page 23

Universal Asynchronous Receiver/Transmitter (UART)
UART Features ............................................................................................................................................ 17–1
UART Functional Description ..................................................................................................................... 17–2
ADSP-SC58x UART Register List............................................................................................................ 17–2
ADSP-SC58x UART Interrupt List ......................................................................................................... 17–3
ADSP-SC58x UART Trigger List ............................................................................................................. 17–4
ADSP-SC58x UART DMA Channel List ................................................................................................. 17–4
UART Block Diagram .............................................................................................................................. 17–5
UART Architectural Concepts .................................................................................................................. 17–5
Internal Interface................................................................................................................................... 17–5
External Interface .................................................................................................................................. 17–6
Hardware Flow Control......................................................................................................................... 17–6
Bit Rate Generation .............................................................................................................................. 17–6
Autobaud Detection .............................................................................................................................. 17–7
UART Debug Features .......................................................................................................................... 17–9
UART Operating Modes.............................................................................................................................. 17–9
UART Mode........................................................................................................................................... 17–10
IrDA SIR Mode...................................................................................................................................... 17–10
Multi-Drop Bus Mode............................................................................................................................ 17–10
UART Data Transfer Modes ................................................................................................................... 17–12
UART Mode Transmit Operation (Core) ............................................................................................ 17–12
UART Mode LIN Break Command .................................................................................................... 17–12
UART Mode Receive Operation (Core)............................................................................................... 17–13
IrDA Transmit Operation ................................................................................................................... 17–14
IrDA Receive Operation...................................................................................................................... 17–14
MDB Transmit Operation................................................................................................................... 17–15
MDB Receive Operation ..................................................................................................................... 17–16
DMA Mode......................................................................................................................................... 17–16
Mixing DMA and Core Modes............................................................................................................ 17–17
Setting Up Hardware Flow Control..................................................................................................... 17–17
UART Event Control ................................................................................................................................. 17–18
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference xxiii