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SEC Architectural Concepts
System Interrupt Groups
System sources can be assigned to groups using the SEC_SCTL[n].GRP bit field. Source groups allow fast context
switching for system interrupts at each SCI. The
groups of unlimited size with a single write operation.
System Interrupt Flow
An enabled and asserted system interrupt source is latched at the SSI and routed to the appropriate SCI based on the
core target select (SEC_SCTL[n].CTG) bit field setting. The SEC priority ordering determines the highest priori-
ty pending system interrupt and the SCI updates the SEC_CPND[n].SID and SEC_CACT[n].PRIO bit field
values. The SCI compares the
SEC_CACT[n]
register).
The priority level register (SEC_CPLVL[n]) determines how many of the MSBs the SEC uses in the comparison.
The priority mask register (SEC_CPMSK[n]) and the group mask register (SEC_CGMSK[n]) determines which
pending interrupt sources participate. If the
the priority of the
SEC_CACT[n]
tem interrupt output is asserted. The source ID register (SEC_CSID[n]) is updated with the
SEC_CPND[n].SID bit field value and forwarded to the connected core.
After the core provides an interrupt acknowledgment, the interrupt source is active, until the SEC completes inter-
rupt service with a write to the SEC_END.SID bit field with the same value. Note the following:
• Interrupt acknowledgement occurs with an MMR write of the
the
SEC_CSID[n]
• Interrupt active status indication is SEC_SSTAT[n].ACT==1.
The following sequence shows the example flow for a single interrupt.
1. The SEC compares the
the
SEC_CPND[n]
2. The SEC copies the
signal.
3. The core reads the
4. The core writes to the
5. The SEC deasserts the interrupt signal and clears the SEC_SSTAT[n].PND bit and sets the
SEC_SSTAT[n].ACT bit of the source going active.
6. The core writes the
7. The SEC clears theSEC_SSTAT[n].ACT bit of the source being ended.
The following sequence shows the example flow for interrupt nesting where interrupt A is a lower priority and oc-
curs earlier than interrupt B.
7–16
SEC_CPND[n]
SEC_CPND[n]
register from the comparison based on the
register.
SEC_CPND[n]
register value to the
register is higher priority, continue.
register value to the
SEC_CPND[n]
register (or core version).
SEC_CSID[n]
SEC_CSID[n]
register (or core version, asserts the acknowledge signal).
of the active interrupt to the
SEC_CSID[n]
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SEC_CGMSK[n]
register allows quick masking of interrupt
register value against the highest priority active source in the
register value is a higher priority (lower value) than
SEC_CSID[n]
SEC_CACT[n]
SEC_CSID[n]
SEC_CPLVL[n]
register or the core version of
register value. If the interrupt in
register and asserts the interrupt
register.
SEC_END
register, the sys-
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