Analog Devices ADSP-SC58 Series Hardware Reference Manual page 442

ADSP-SC58x DMC Register Descriptions
Table 10-18: DMC_EFFCTL Register Fields (Continued)
Bit No.
(Access)
19:16 NUMREF
(R/W)
15 PRECBANK7
(R/W)
14 PRECBANK6
(R/W)
10–36
Bit Name
Number of Refresh Commands.
The DMC_EFFCTL.NUMREF bits select the number of auto-refresh commands that
the DMC can accumulate if postpone refresh is enabled (DMC_CTL.PPREF =1). The
number of auto-refresh commands that can accumulate depends on whether the DMC
is in DDR2 or LPDDR mode as selected by the DMC_CTL.LPDDR bit. In LPDDR
mode, the DMC can accumulate up to four auto-refresh commands. In DDR2 mode,
the DMC may accumulate up to eight auto-refresh commands.
Note 1: By default, accumulated auto-refresh commands are issued after counting four
idle cycles.
Note 2: This value is ignored if DMC_CTL.PPREF is not set.
Precharge Bank 7.
The DMC_EFFCTL.PRECBANK7 bit enables precharge (closes the page) of bank 7
after each transfer if the DMC precharge feature is enabled (DMC_CTL.PREC =1).
Note: The (DMC_CTL.PREC) takes precedence over value in this register. If
(DMC_CTL.PREC =1) then all banks are precharged.
Precharge Bank 6.
The DMC_EFFCTL.PRECBANK6 bit enables precharge (closes the page) of bank 6
after each transfer if the DMC precharge feature is enabled (DMC_CTL.PREC =1).
Note: The (DMC_CTL.PREC) takes precedence over value in this register. If
(DMC_CTL.PREC =1) then all banks are precharged.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No Refresh Commands Accumulate
1 1 Refresh Command May Accumulate
2 2 Refresh Commands May Accumulate
3 3 Refresh Commands May Accumulate
4 4 Refresh Commands May Accumulate
5 5 Refresh Commands May Accumulate
6 6 Refresh Commands May Accumulate
7 7 Refresh Commands May Accumulate
8 8 Refresh Commands May Accumulate
0 Disable Precharge Bank 7
1 Enable Precharge Bank 7
0 Disable Precharge Bank 6
1 Enable Precharge Bank 6