Analog Devices ADSP-SC58 Series Hardware Reference Manual page 816

Table 17-11: UART_CTL Register Fields (Continued)
Bit No.
(Access)
22 FCPOL
(R/W)
19 SB
(R/W)
18 FFE
(R/W)
17 FPE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Flow Control Pin Polarity.
The UART_CTL.FCPOL bit selects the polarities of the UART_CTS and
UART_RTS pins. When the UART_CTL.FCPOL bit is cleared, the UART_RTS and
UART_CTS pins are active low, and the UART is halted when the UART_RTS and
UART_CTS pin state is high. When UART_CTL.FCPOL bit is set, the UART_RTS
and UART_CTS pins are active high, and the UART is halted when the UART_RTS
and UART_CTS pin state is low.
Set Break.
If set, the UART_CTL.SB bit forces the UART_TX pin to low asynchronously, re-
gardless of whether or not data is currently transmitted. This bit functions even when
the UART clock is disabled. Because the UART_TX pin normally drives high, it can be
used as a flag output pin, if the UART is not used. (For example, if
UART_CTL.TPOLC is cleared, drive UART_TX pin low; or if UART_CTL.TPOLC
is set, drive UART_TX pin high.)
Force Framing Error on Transmit.
The UART_CTL.FFE bit is intended for test purposes. This bit is useful for debug-
ging software, especially in loopback mode.
Force Parity Error on Transmit.
The UART_CTL.FPE bit is intended for test purposes. This bit is useful for debug-
ging software, especially in loopback mode.
ADSP-SC58x UART Register Descriptions
Description/Enumeration
0 Active low CTS/RTS
1 Active high CTS/RTS
0 No force
1 Force TX pin to 0
0 Normal operation
1 Force error
0 Normal operation
1 Force parity error
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