Table of Contents
Advertisement
PORT Features
PORT Features
The PORTs include the following features:
• Input mode, output mode, and open-drain mode of GPIO operation
• Port multiplexing controlled on a pin-by-pin basis
• No external glue hardware required for unused pins
• All port pins provide interrupt request functionality
• Byte-wide pin-to-interrupt request assignment
PORT Functional Description
The number of ports and each's composition are defined in the processor datasheet. Each port has a dedicated set of
MMR registers that control pin functions and operates in general-purpose I/O (GPIO) mode by default, as control-
led by the port-specific
specific GPIO pin on the specified port.
Input Mode, Output Mode, and Open-Drain Mode of GPIO Operation
At reset, every GPIO pin defaults to input mode with the input drivers disabled. To enable any GPIO input
driver, set the bits corresponding to the individual pins in the appropriate input enable register
(PORT_INEN).
The GPIO output drivers are enabled by setting the corresponding bits in the direction registers
(PORT_DIR).
The PORT can use every GPIO in open-drain mode by clearing the respective bit in the
ter or setting the respective bit in the
PORT_INEN
register. Read from the
Port Multiplexing Controlled on Pin-by-Pin Basis
Each port has two dedicated MMRs that control the port multiplexing, the 16-bit function enable
(PORT_FER) registers and the 32-bit port multiplexing (PORT_MUX) registers.
All Port Pins Provide Interrupt Functionality
Pin interrupts are completely decoupled from GPIO functionality. Pins are connected to the system event con-
troller (SEC) via the PINTx modules, each of which is configurable in terms of which port pins are sensed for
interrupt generation.
14–2
register. Each bit in this register, as well as the other PORT MMRs, represents a
PORT_FER
PORT_DATA_CLR
PORT_DATA
register. Then, set the corresponding bit in the
register to obtain the status from the pin.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
regis-
PORT_DATA
Advertisement
Table of Contents
