Analog Devices ADSP-SC58 Series Hardware Reference Manual page 817

ADSP-SC58x UART Register Descriptions
Table 17-11: UART_CTL Register Fields (Continued)
Bit No.
(Access)
16 STP
(R/W)
15 EPS
(R/W)
14 PEN
(R/W)
13 STBH
(R/W)
12 STB
(R/W)
17–30
Bit Name
Sticky Parity.
The UART_CTL.STP bit controls whether the parity is generated by hardware based
on the data bits or whether it is set to a fixed value. If this bit is cleared, the hardware
calculates the parity bit value based on the data bits. Then, the EPS bit determines
whether odd or even parity mode is chosen. If this bit is set, odd parity is used. That
means that the total count of logical-1 data bits including the parity bit must be an
odd value. Even parity is chosen by UART_CTL.STP cleared and UART_CTL.EPS
set. Then, the count of logical-1 bits must be a even value. If the UART_CTL.STP
bit is set, hardware parity calculation is disabled. In this case, the sent and received par-
ity equals the inverted UART_CTL.EPS bit.
Even Parity Select.
Parity Enable.
The UART_CTL.PEN bit enables parity transmission and parity check. The
UART_CTL.PEN bit inserts one additional bit between the most significant data bit
and the first stop bit. The polarity of this so-called parity bit depends on data and the
UART_CTL.STP and UART_CTL.EPS control bits. Both transmitter and receiver
calculate the parity value. The receiver compares the received parity bit with the ex-
pected value and issues a parity error if they do not match. If the UART_CTL.PEN
bit is cleared, the UART_CTL.STP and the UART_CTL.EPS bits are ignored.
Stop Bits (Half Bit Time).
Stop Bits.
The UART_CTL.STB bit controls how many stop bits are appended to transmitted
data.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No forced parity
1 Force (Stick) parity to defined value (if PEN=1)
0 Odd parity
1 Even parity
0 Disable
1 Enable parity transmit and check
0 0 half-bit-time stop bit
1 1 half-bit-time stop bit
0 1 stop bit
1 2 stop bits