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SMC Definitions
Read setup time
The time between the beginning of a memory cycle (SMC_AMS0 signal low) and the read-enable assertion
(SMC_ARE signal low).
Read hold time
The time between read-enable deassertion (SMC_ARE signal high) and the end of the memory cycle (SMC_AMS0
signal high).
Read access
The time between read-enable assertion (SMC_ARE signal low) and deassertion (SMC_ARE signal high).
Write setup time
The time between the beginning of a memory cycle (SMC_AMS0 signal low) and the write-enable assertion
(SMC_AWE signal low).
Write hold time
The time between write-enable deassertion (SMC_AWE signal high) and the end of the memory cycle (SMC_AMS0
signal high).
Write access
The time between write-enable assertion (SMC_AWE signal low) and deassertion (SMC_AWE signal high).
The SMC provides another register for defining more timing characteristics of control signals by programming the
extended
SMC_B0TIM
–
SMC_B3TIM
timing registers. These registers contain bits to program following timing
characteristics.
Pre-setup time
The number of cycles the SMC_AMS0 signal is asserted before the SMC_AOE signal is asserted.
Pre-access time
The number of cycles inserted after the SMC_AOE signal is deasserted and before the SMC_ARE signal is asserted
for the next access.
Memory idle time
The number of bus idle cycles between the SMC_AMS0 deasserting edge and next asserting edge.
11–2
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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