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PHY Control 4 Register
The
DMC_PHY_CTL4
CLKDIS (R/W)
Clock Disable
Figure 10-34: DMC_PHY_CTL4 Register Diagram
Table 10-44: DMC_PHY_CTL4 Register Fields
Bit No.
(Access)
2
CLKDIS
(R/W)
1:0
DDRMODE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register controls programmable PHY features.
15
14
13
12
11
0
0
0
0
0
31
30
29
28
27
0
0
0
0
0
Bit Name
Clock Disable.
The DMC_PHY_CTL4.CLKDIS bit enables and disables the DDR clock.
DDR Mode Select.
The DMC_PHY_CTL4.DDRMODE bit field selects between the various DDR modes.
Not all modes are available on all processors.
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
26
25
24
23
22
21
20
19
0
0
0
0
0
0
0
0
Description/Enumeration
0 Enable Clock
1 Disable Clock
0 DDR3 Mode
1 DDR2 Mode
2 Reserved
3 LPDDR Mode
ADSP-SC58x DMC Register Descriptions
2
1
0
0
0
0
DDRMODE (R/W)
DDR Mode Select
18
17
16
0
0
0
10–75
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