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Asynchronous Flash Mode
When the access selected mode is asynchronous flash (SMC_B0CTL.MODE =01), external bank accesses operate the
same as in standard asynchronous mode, except for the pin configuration. Use this mode when accessing burst
devices in non-read array modes.
Asynchronous Page Mode
When asynchronous page mode access is selected (SMC_B0CTL.MODE =10), asynchronous page reads are enabled.
The SMC module supports page sizes of 4, 8 and 16 words. When performing a page mode read, the first access in
the page proceeds according to the read access time configured in
and the subsequent reads in that page have a period equal to the page wait states programmed in the
register. Besides the start of the setup phase, the read address is incremented at the start of every page cycle.
The SMC module supports page mode access only for back-to-back accesses, such as cache line fills (16 words), 64-
bit instruction reads (4 words), and DMA reads. It treats write accesses in asynchronous page mode as simple asyn-
chronous flash write accesses.
SMC Event Control
SMC event control consists of recording the status of SMC errors. Accesses to reserved locations and writes to read-
only registers result in bus errors. The SMC translates bus errors into internal SCB crossbar errors which get transla-
ted into interrupts. To report errors occurring in the slave memory devices (for both this memory interface and the
MMR interface), the core combines the SCB crossbar response signals. This combination generates a combined er-
ror signal indication which is routed to the fault management unit.
SMC Programmable Timing Characteristics
This section describes the programmable timing characteristics for the SMC. Timing relationships depend on the
programming of the SMC bank registers, whether initiation is from the core or from DMA. The relationships also
depend on the sequence of transactions (read followed by read, read followed by write, and others).
All memory control, address, and data signals are driven out of the chip based on the falling edge of the
NOTE:
CLKOUT signal. The CLKOUT signal is SCLK0_0 on the chip pins (pad delayed).
Asynchronous SRAM Reads and Writes
The Basic Asynchronous SRAM Write Followed by Read figure shows a basic single write and read operation to an
external device with the SMC programmed in asynchronous SRAM mode.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SMC_B0TIM
register. This access opens the page
SMC Operating Modes
SMC_B0ETIM
11–7
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