Analog Devices ADSP-SC58 Series Hardware Reference Manual page 285

ADSP-SC58x SEC Register Descriptions
Table 7-16: SEC_FCTL Register Fields (Continued)
Bit No.
(Access)
12 CMS
(R/W)
7 FIEN
(R/W)
6 SREN
(R/W)
5 TOEN
(R/W)
4 FOEN
(R/W)
1 RESET
(R0/W)
7–40
Bit Name
COP Mode Select.
The SEC_FCTL.CMS selects the SEC mode for handling fault input. In COP mode,
the SEC toggles the COP pin to indicate that no fault is active and ceases toggling the
pin to indicate that a fault is active. In fault mode, the SEC deasserts the fault pin (=0)
and fault_b pin (=1) when no fault is active and asserts the fault pin (=1) and fault_b
pin (=0) when a fault is active. Not all processors feature both the fault and fault_b
pins. Refer to the product data sheet for details.
Fault Input Enable.
The SEC_FCTL.FIEN bit enables the SEC to sample fault input. If
SEC_FCTL.FIEN is set (=1), a fault indication from an external device sets the
SEC_FSTAT.ACT bit and SEC_FSID.FEXT bit.
System Reset Enable.
The SEC_FCTL.SREN bit enables the SEC to issue a system reset request when a
fault becomes active.
Trigger Output Enable.
The SEC_FCTL.TOEN bit enables the SEC to produce trigger output when a fault
becomes active.
Fault Output Enable.
The SEC_FCTL.FOEN bit enables the SEC to indicate fault status, according to the
SEC_FCTL.CMS bit configuration.
Reset.
Setting the SEC_FCTL.RESET bit resets ALL SEC registers to their default values.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Fault Mode
1 COP Mode
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 No Action
1 Reset