Analog Devices ADSP-SC58 Series Hardware Reference Manual page 327

Sharc+ processor
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ADSP-SC58x GICCPU Register Descriptions
CPU Interface Control Register (ICCICR)
The
GICCPU_CTL
register enables the signaling of interrupts to the target processors. In a GIC that implements
the Security Extensions, provides additional global controls for handling Secure interrupts.
VALUE[31:16] (R/W)
Control N
Figure 7-50: GICCPU_CTL Register Diagram
Table 7-52: GICCPU_CTL Register Fields
Bit No.
(Access)
31:0
VALUE
(R/W)
7–82
15
0
VALUE[15:0] (R/W)
Control N
31
0
Bit Name
Control N.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0

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