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Table 16-13: SPI Transmit Control Register
Bits
SPI_TXCTL.TEN
SPI_TXCTL.TTI
SPI_TXCTL.TWCEN
SPI_TXCTL.TDR
SPI_TXCTL.TDU
SPI_TXCTL.TRWM
SPI_TXCTL.TUWM
Table 16-14: SPI DLY Control Register
Bits
SPI_DLY.LAGX
SPI_DLY.LEADX
SPI_DLY.STOP
The multiple I/O mode (SPI_CTL.MIOM) bits are partially ignored:
• The command (opcode) is transmitted using either just one or the number of pins specified by the
SPI_CTL.MIOM bits, depending on SPI_MMRDH.CMDPINS bit setting.
• The address is then transmitted using either just one or the number of pins specified by the SPI_CTL.MIOM
bits, depending on SPI_MMRDH.ADRPINS bit setting.
• The data is always read with the number of pins specified by the SPI_CTL.MIOM bits.
Set the SPI module enable bits SPI_CTL.EN last after configuring all registers.
NOTE:
Use the following programming guidelines for memory-mapped mode:
• The SPI memory-mapped hardware does not check the flash status before initiating the access. It assumes that
SPI memory is always able to respond to a read access. Befor enabling memory-mapped mode (for example,
setting the SPI_CTL.MMSE bit) ensure that SPI flash is ready for a read access. When using non-memory-
mapped mode, a write-complete status can be examined prior to enabling the SPI in memory-mapped mode.
(See the write in progress bit in the SPI flash memory status register.) Also, immediately after initial power-up,
SPI memory devices can be inaccessible for a vendor-specified period.
• When SPI is enabled in memory-mapped mode, attempts to communicate with the SPI device using legacy
methods are blocked. Legacy methods include any direct access made to the transmit or receive FIFOs, whether
initiated by DMA or by a processor MMR access.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Typical values to set
Description
1
Transmit channel enable
1
Transmit transfer initiation disable
0
Transmit word counter disable
0
Transmit data request disable
0
Send last word when TFIFO is empty
0
Transmit FIFO regular watermark
0
Transmit FIFO urgent watermark disable
Typical values to set
Description
1
Extended lag timing
1
Extended lead timing
3
Stop bit between the transfers
Memory-Mapped Mode (SPI2 only)
Comments
See Flash data sheet for CS (for
example. SSEL) timing specs
Can be set to 1 at lower SPI clock
frequencies.
16–27
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