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ADSP-SC58x SMPU Register Descriptions
SMPU Control Secure Accesses Register
The
SMPU_SECURECTL
settings includes error generation and read/write security.
WSECDIS (R/W)
Secure Write Transaction Disable
WNSEN (R/W)
Non-secure Write Transaction Enable
RSECDIS (R/W)
Secure Read Transaction Disable
RNSEN (R/W)
Non-secure Read Transaction Enable
LOCK (R/W)
Lock Bit
Figure 13-16: SMPU_SECURECTL Register Diagram
Table 13-20: SMPU_SECURECTL Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
11
WSECDIS
(R/W)
10
WNSEN
(R/W)
13–32
register provides the bits required to set up the security settings for the processor. These
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
Lock Bit.
When the SMPU_SECURECTL.LOCK bit is set and the global lock signal is asserted
from the SPU, the
disabled only when the global lock signal becomes deasserted again.
Secure Write Transaction Disable.
The SMPU_SECURECTL.WSECDIS bit disables secure write transactions.
Non-secure Write Transaction Enable.
The SMPU_SECURECTL.WNSEN bit enables non-secure write transactions.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
SMPU_SECURECTL
0
SMPU_SECURECTL
1
SMPU_SECURECTL
0 Enable secure write transactions
1 Disable secure write transactions
0 Disable non-secure writes
1 Enable non-secure writes
SBEDIS (R/W)
Security Violation Bus Error Disable
SBETYPE (R/W)
Security Violation Bus Error Type
SINTEN (R/W)
Security Violation Interrupt Enable
RLOCK (R/W)
Secure Region Registers Lock Bit
register is write-protected. Write-protection is
is not write-protected
is write-protected
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