Analog Devices ADSP-SC58 Series Hardware Reference Manual page 17

Sharc+ processor
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Memory Writes......................................................................................................................................... 13–4
Memory Reads ......................................................................................................................................... 13–4
ID Comparison ........................................................................................................................................ 13–5
Memory Region........................................................................................................................................ 13–8
SMPU Definitions ................................................................................................................................... 13–9
SMPU Block Diagram............................................................................................................................ 13–10
SMPU Architectural Concepts ............................................................................................................... 13–10
SMPU Operating Modes ........................................................................................................................... 13–11
SMPU Interrupt Signals ............................................................................................................................ 13–11
SMPU Status and Error Signals ................................................................................................................. 13–12
SMPU Programming Example................................................................................................................... 13–12
ADSP-SC58x SMPU Register Descriptions .............................................................................................. 13–13
Bus Error Address Register .................................................................................................................... 13–15
Bus Error Details Register ..................................................................................................................... 13–16
SMPU Control Register ........................................................................................................................ 13–17
Exclusive Access IDn Address ................................................................................................................ 13–19
Exclusive Access Status .......................................................................................................................... 13–20
Interrupt Address Register ..................................................................................................................... 13–21
Interrupt Details Register ...................................................................................................................... 13–22
Region n Address Register ..................................................................................................................... 13–23
Region n Control Register ..................................................................................................................... 13–24
SMPU Revision ID Register .................................................................................................................. 13–27
Region n ID A Register ......................................................................................................................... 13–28
Region n ID B Register ......................................................................................................................... 13–29
Region n ID Mask A Register ................................................................................................................ 13–30
Region n ID Mask B Register ................................................................................................................ 13–31
SMPU Control Secure Accesses Register ............................................................................................... 13–32
Region n Control Secure Accesses Register ............................................................................................ 13–34
SMPU Status Register ........................................................................................................................... 13–35
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
xvii

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