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Channel Timing Control Unit
Figure 19-8: Channel Outputs in Dependent Mode for Pulse Mode = 00
Figure 19-9: Channel Outputs in Dependent Mode for Pulse Mode = 01
The following pair of figures shows the high and low-side outputs for the case with zero and non-zero dead-time for
PWM_ACTL.PULSEMODEHI =10 and 11. In the figures, DUTY0 is the value programmed into
ter and DUTY1 is the value programmed into the
both signals are active high. The channel dead-time registers hold the value DT.
Using dead time, the guidelines for programming the duty-cycle registers in pulse modes 10 and 11 given
NOTE:
in
Duty Cycle and Pulse Positioning Control
Pulse mode 10: PWM_xH0 – DT > PWM_xH1 + DT
Pulse mode 11: PWM_xH0 + DT < PWM_xH1 – DT
19–16
DT
DUTY0
DT
Zero Dead-Time
PWM_AH
PWM_AL
Non-zero Dead-Time
PWM_AH
PWM_AL
PULSEMODE = 00
DUTY1
DT
DUTY0
DT
Zero Dead-Time
PWM_AH
PWM_AL
Non-zero Dead-Time
PWM_AH
PWM_AL
PULSEMODE = 01
PWM_AH1
are modified as follows:
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DT
DT
DT
DT
register. PWM_CHANCFG.POLAH is 1 indicating that
PWM_AH0
regis-
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