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9. If the receive pipe fills up due to unavailability of DMA grants, the transmit pipe stalls until the pipe is drained.
If the transmit pipe fills up, the SPI stops requesting for DMA writes. If the value in
write-requests to DMA stop. However, data already written into the transmit FIFO is sent, and read requests to
DMA continue until the receive data is read from the receive FIFO.
10. The SPI then generates the programmed clock pulses on SPI_CLK and simultaneously shifts data out of
SPI_MOSI while shifting data in from SPI_MISO. For receive transfers, the value in the shift register is loa-
ded into the
SPI_RFIFO
SPI_TFIFO
register is loaded into the shift register at the start of the transfer.
Configuring DMA Slave Mode Operation
This mode occurs when the SPI is enabled as a slave and the DMA engine is configured to transmit or receive data.
A transition of the SPI_SS signal to the active-low state triggers the start of a transfer. Or, the first active edge of
SPI_CLK triggers the start of a transfer, depending on the state of the SPI_CTL.CPHA bit. The following steps
illustrate the SPI receive or transmit DMA sequence in an SPI slave (in response to a master command). The SPI
supports a receive DMA channel and a transmit DMA channel.
1. Write to the appropriate DMA registers to enable the SPI DMA channel and configure the necessary work
units, access direction, word count, and so on.
2. Write to the SPI_CTL, SPI_RXCTL, and
the same as the mode configured in the SPI master.
3. If the receive channel is enabled (SPI_RXCTL.REN is asserted), the following actions occur:
a. Once the slave select input is active, the slave starts receiving and transmitting data on active SPI_CLK
edges.
b. The value in the shift register is loaded into the
c. Once
SPI_RFIFO
d. Upon a DMA grant, the DMA engine reads a word from the receive FIFO and writes to memory.
e. As long as there is data in the receive FIFO, the SPI slave continues to request a DMA write to memory.
The DMA engine continues to read a word from the FIFO and writes to memory until the
counts to zero. The SPI slave continues receiving words on active SPI_CLK edges as long as the SPI_SS
input is active.
f. If the data collected in the receive pipe breaches the set level, and the DMA engine cannot keep up with
the receive rate, the slave can deassert the SPI_RDY signal. This signaling throttles the master. The re-
ceive pipe level is set according to the SPI_CTL.FCWM field. The signal is deasserted as the DMA drains
the receive FIFO. Alternatively, the SPI can use the SPI_RXCTL.RDO bit to decide when the incoming
data is discarded or overwritten into the receive FIFO (when SPI_CTL.FCEN is inactive).
4. If the transmit channel is enabled (SPI_TXCTL.TEN is asserted), the following actions occur:
a. The SPI requests a DMA read from memory.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register at the end of the transfer. For transmit transfers, the value in the
SPI_TXCTL
has valid data, it requests a write from DMA to memory.
registers to define the mode of the serial link to be
register at the end of the transfer.
SPI_RFIFO
SPI Programming Concepts
SPI_RWC
expires, further
SPI_RWC
16–33
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