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Peripherals
inputs. Since integration provides relative position, some devices also feature a zero-position input (zero marker).
The GP counter can use the zero position input feature to establish a reference point for verifying that the acquired
position does not drift over time. In addition, the GP counter can use the incremental position information to de-
termine speed, if the time intervals are measured.
Figure 1-22: CNT System Diagram
ADC Control Module (ACM)
The processor includes an
between the processor and an analog-to-digital converter (ADC). The processor initiates analog-to-digital conver-
sions, based on either external or internal events.
System MMR Write-Protection (WP65) from SPU
Enable Secure Peripheral (SECUREP65) from SPU
Figure 1-23: ACM System Diagram
Controller Area Network (CAN)
The processor contains a
protocol is an asynchronous communications protocol used in both industrial and automotive control systems. The
CAN protocol is compatible with the control applications. It can communicate reliably over a network and incorpo-
rates CRC checking, message error tracking, and fault node confinement.
Figure 1-24: CAN System Diagram
1–12
CNT
PB_11 Pin
CNT0_ZM
PB_12 Pin
CNT0_UD
PB_14 Pin
CNT0_DG
Clocked by SCLK0_0
ADC Control Module (ACM)
PC_12 Pin
PD_13 Pin
PC_14 Pin
PC_15 Pin
PD_00 Pin
PD_01 Pin
Clocked by SCLK0_0
Controller Area Network (CAN)
CAN1_TX
PB_09 Pin
PB_10 Pin
CAN1_RX
PC_07 Pin
CAN0_TX
PC_08 Pin
CAN0_RX
Clocked by CDU0_CLKO4
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CNT0_STAT Status Interrupt to SEC/GIC
CNT0_STAT Trigger to TRU Slaves
System MMR Write-Protection (WP57) from SPU
Enable Secure Peripheral (SECUREP57) from SPU
that provides an interface that synchronizes the controls
ACM
ACM0_T0
ACM Event Miss Interrupt to SEC/GIC
ACM0_A0
ACM Event Complete Interrupt to SEC/GIC
ACM0_A1
ACM Event Complete Trigger to TRU Slaves
ACM0_A2
ACM Trigger Inputs (ACM0_TRIG3:2) from TRU Masters
ACM0_A3
ACM0_A4
SPORT0 Signals Connect to External ADC via DAI Pins
module based on the CAN 2.0B (active) protocol. This
CAN
CANx Receive Interrupts to SEC/GIC
CANx Transmit Interrupts to SEC/GIC
CANx Status Interrupts to SEC/GIC
System MMR Write-Protection (WP8:7) from SPU
Enable Secure Peripheral (SECUREP8:7) from SPU
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