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Horizontal Delay Count Register
The
register contains the number of clock cycles to delay after the assertion of EPPI_FS1 is detected
EPPI_HDLY
before starting to read or write data.
Figure 18-26: EPPI_HDLY Register Diagram
Table 18-60: EPPI_HDLY Register Fields
Bit No.
(Access)
15:0
VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
0
0
0
VALUE (R/W)
Horizontal Delay Count
31
30
29
0
0
0
Bit Name
Horizontal Delay Count.
The EPPI_HDLY.VALUE holds the number of EPPI_CLK cycles to delay after as-
sertion of EPPI_FS1 before starting to read or write data.
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x EPPI Register Descriptions
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
18–73
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