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ADSP-SC58x DMC Register Descriptions
Timing 0 Register
The
register selects timing parameters for DMC operation to corresponding with parameters of the
DMC_TR0
SDRAM device that is used in the system. The timing registers must be programmed to match the device for correct
operation of the SDRAM and must be programmed before initializing the SDRAM. Note that all values for bit
fields in
DMC_TR0
are in increments of clock cycle time (t
TRAS[3:0] (R/W)
Timing Row Active Time
TRP (R/W)
Timing RAS Precharge
TMRD (R/W)
Timing Mode Register Delay
TRC (R/W)
Timing Row Cycle
Figure 10-25: DMC_TR0 Register Diagram
Table 10-34: DMC_TR0 Register Fields
Bit No.
(Access)
31:28
TMRD
(R/W)
25:20
TRC
(R/W)
16:12
TRAS
(R/W)
11:8
TRP
(R/W)
10–64
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
25
0
0
0
0
0
0
Bit Name
Timing Mode Register Delay.
The DMC_TR0.TMRD field selects the set-to-active timing parameter (t
is the number of clock cycles that occur after the mode registers in the SDRAM are set
and before the next command is issued.
Timing Row Cycle.
The DMC_TR0.TRC field selects the active-to-active time (t
mum number of clock cycles that occur from an active command to the next active
command in the same bank.
Timing Row Active Time.
The DMC_TR0.TRAS field selects the active-to-precharge time (t
number of clock cycles that occur from an active command until a precharge com-
mand is allowed.
Timing RAS Precharge.
The DMC_TR0.TRP field selects the precharge-to-active time (t
number of clock cycles that occur while the SDRAM recovers from a precharge com-
mand and becomes ready to accept the next active command.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
).
CK
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
Description/Enumeration
1
0
0
0
TRCD (R/W)
Timing RAS to CAS Delay
TWTR (R/W)
Timing Write to Read
16
0
0
TRAS[4] (R/W)
Timing Row Active Time
), which is the mini-
RC
), which
MRD
), which is the
RAS
), which is the
RP
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