Table of Contents
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Dynamic Coefficient Processing Notes ................................................................................................... 52–12
Writing to Local Memory ....................................................................................................................... 52–13
Reading from Local Memory .................................................................................................................. 52–13
Single Step Mode.................................................................................................................................... 52–13
Save Biquad State of the IIR ................................................................................................................... 52–13
Programming Example ........................................................................................................................... 52–14
ADSP-SC58x IIR Register Descriptions ................................................................................................... 52–15
Chain Pointer Register .......................................................................................................................... 52–16
Coefficient Buffer Index Register ........................................................................................................... 52–17
Coefficient Buffer Length Register ........................................................................................................ 52–18
Coefficient Index Modifier Register ....................................................................................................... 52–19
Global Control Register ......................................................................................................................... 52–20
Channel Control Register ...................................................................................................................... 52–22
IIR Debug Address Register ................................................................................................................... 52–23
IIR Debug Control Register .................................................................................................................. 52–24
IIR Debug Read Data High Register ..................................................................................................... 52–25
IIR Debug Read Data Low Register ...................................................................................................... 52–26
IIR Debug Write Data High Register .................................................................................................... 52–27
IIR Debug Write Data Low Register ...................................................................................................... 52–28
DMA Status Register ............................................................................................................................. 52–29
Input Buffer Base Register ..................................................................................................................... 52–31
Input Data Index Register ..................................................................................................................... 52–32
Input Data Buffer Length Register ........................................................................................................ 52–33
Input Data Index Modifier Register ....................................................................................................... 52–34
MAC Status Register ............................................................................................................................. 52–35
Output Buffer Base Register .................................................................................................................. 52–36
Output Data Buffer Index Register ........................................................................................................ 52–37
IIR Output Data Buffer Length Register ............................................................................................... 52–38
IIR Output Data Index Modifier Register ............................................................................................. 52–39
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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