Analog Devices ADSP-BF535 Blackfin Manuals

Manuals and User Guides for Analog Devices ADSP-BF535 Blackfin. We have 1 Analog Devices ADSP-BF535 Blackfin manual available for free PDF download: Hardware Reference Manual

Analog Devices ADSP-BF535 Blackfin Hardware Reference Manual

Analog Devices ADSP-BF535 Blackfin Hardware Reference Manual (1022 pages)

Brand: Analog Devices | Category: Computer Hardware | Size: 11.87 MB

Table of Contents

Hardware Reference
1
Table of Contents
3
Preface

43
- Purpose of this Manual
  43
- Intended Audience
  43
- Manual Contents
  44
- What's New in this Manual
  48
- Technical Support
  48
- Supported Processors
  49
- Product Information
  50
  - Analog Devices Web Site
    50
  - Engineerzone
    51
- Notation Conventions
  52
- Register Diagram Conventions
  53
Introduction

55
- ADSP-BF535 Peripherals
  55
- ADSP-BF535 Core Architecture
  56
- Memory Architecture
  59
  - Internal (On-Chip) Memory
    61
  - External (Off-Chip) Memory
    62
- Pci
  62
- I/O Memory Space
  64
- Event Handling
  64
- DMA Support
  65
- External Bus Interface Unit
  66
  - PC133 SDRAM Controller
    66
  - Asynchronous Controller
    67
- PCI Interface
  67
  - PCI Host Function
    68
  - PCI Target Function
    69
- USB Port
  69
- Real-Time Clock
  69
- Watchdog Timer
  70
- Timers
  71
- Serial Ports (Sports)
  71
- Serial Peripheral Interface (SPI) Ports
  73
- UART Ports
  74
- Programmable Flags
  75
- Low Power Operation
  76
- Clock Signals
  77
  - Boot Modes
    78
  - Instruction Set Description
    78
  - Development Tools
    78
Computational Units

81
- Using Data Formats
  83
  - Binary String
    83
  - Unsigned
    84
  - Signed Numbers: Two's-Complement
    84
- Register Files
  85
  - Data Register File
    86
  - Accumulator Registers
    86
  - Pointer Register File
    86
  - DAG Register Set
    87
  - Register File Instruction Summary
    88
- Data Types
  90
  - Data Formats
    91
  - Endianess
    92
  - ALU Data Types
    92
  - Multiplier Data Types
    93
  - Shifter Data Types
    94
  - Arithmetic Formats Summary
    95
  - Using Multiplier Integer and Fractional Formats
    96
- Rounding Multiplier Results
  98
  - Unbiased Rounding
    98
  - Biased Rounding
    100
  - Truncation
    101
- Special Rounding Instructions
  101
- Using Computational Status
  102
- Arithmetic Status Register (ASTAT)
  103
- Arithmetic Logic Unit (ALU)
  104
  - ALU Operations
    104
    
    Quad 16-Bit Operations
    105
    
    Single 16-Bit Operations
    105
    
    Dual 32-Bit Operations
    107
    
    Single 32-Bit Operations
    107
  - ALU Instruction Summary
    108
  - ALU Data Flow Details
    108
    
    Dual 16-Bit Cross Options
    110
    
    ALU Status Signals
    111
  - ALU Division Support Features
    111
  - Special SIMD Video ALU Operations
    112
- Multiply Accumulators (Multipliers)
  112
  - Multiplier Operation
    113
    
    Placing Multiplier Results in Multiplier Accumulator Registers
    114
    
    Rounding or Saturating Multiplier Results
    114
    
    Multiplier Instruction Options
    115
    
    Multiplier Instruction Summary
    115
    
    Saturating Multiplier Results on Overflow
    115
    
    Multiplier Data Flow Details
    118
    
    Multiply Without Accumulate
    120
    
    Special 32-Bit Integer MAC Instruction
    122
    
    Dual MAC Operations
    123
  - Barrel Shifter (Shifter)
    124
    
    Shifter Operations
    124
    
    Immediate Shifts
    125
    
    Two Operand Shifts
    125
    
    Immediate Shifts
    126
    
    Register Shifts
    126
    
    Three Operand Shifts
    126
    
    Register Shifts
    127
    
    Bit Test, Set, Clear, Toggle
    128
    
    Field Extract and Field Deposit
    128
    
    Shifter Instruction Summary
    128
Operating Modes and States

129
- User Mode
  131
  - Protected Resources and Instructions
    132
  - Protected Memory
    133
  - Entering User Mode
    133
    
    Example Code to Enter User Mode Upon Reset
    133
    
    Return Instructions that Invoke User Mode
    133
- Supervisor Mode
  134
  - Non-OS Environments
    135
    
    Example Code to Stay in Supervisor Mode Coming out of Reset
    136
- Emulation Mode
  137
- Idle State
  137
  - Example Code for Transition to Idle State
    138
- Reset State
  138
- System Reset and Power-Up Configuration
  140
  - Hardware Reset
    141
  - System Reset Configuration Register (SYSCR)
    142
  - Software Resets and Watchdog Timer
    142
  - Software Reset Register (SWRST)
    144
  - Core Only Software Reset
    145
- Booting Methods
  145
Program Sequencer

147
- Sequencer Related Registers
  149
- Instruction Pipeline
  153
- Branches and Sequencing
  155
  - Direct Short and Long Jumps
    157
  - Direct Call
    157
  - Indirect Branch and Call
    157
  - PC-Relative Indirect Branch and Call
    158
  - Condition Code Flag
    158
    
    Conditional Branches
    159
    
    Conditional Register Move
    159
  - Branch Prediction
    160
- Loops and Sequencing
  161
- Events and Sequencing
  163
- Event Controller Registers
  177
- Global Enabling/Disabling of Interrupts
  180
- Event Vector Table
  181
  - Emulation
    181
  - Reset
    181
  - NMI (Non-Maskable Interrupt)
    184
  - Exceptions
    184
  - Exceptions While Executing an Exception Handler
    189
- Hardware Error Interrupt
  190
  - Core Timer
    192
  - General-Purpose Interrupts (IVG7-IVG15)
    192
- Servicing Interrupts
  192
- Interrupts with and Without Nesting
  194
Data Address Generators

207
- Addressing with Dags
  210
  - Frame and Stack Pointers
    211
  - Addressing Circular Buffers
    212
  - Addressing with Bit-Reversed Addresses
    215
- Indexed Addressing with Index and Pointer Registers
  215
- Modifying DAG and Pointer Registers
  218
- Memory Address Alignment
  219
- DAG Instruction Summary
  222
Memory

227
- Terminology
  227
- Memory Architecture
  231
  - Internal Memory
    235
    
    Overview of L1 Data SRAM
    236
    
    Overview of L1 Instruction SRAM
    236
    
    Overview of On-Chip L2 Memory
    237
    
    Overview of Scratchpad Data SRAM
    237
  - Level 1 Memory
    238
  - Data Memory Control Register (DMEM_CONTROL)
    239
- Instruction Memory Control Register (IMEM_CONTROL)
  240
- L1 Instruction Memory
  240
  - L1 Instruction SRAM
    240
- L1 Instruction Cache
  243
  - Cache Lines
    243
    
    Cache Hits and Misses
    245
    
    Cache Line Fills
    246
    
    Line Fill Buffer
    247
    
    Cache Line Replacement
    248
    
    Non-Cacheable Accesses
    248
- Instruction Cache Management
  250
  - Instruction Cache Locking
    250
  - Instruction Cache Invalidation
    251
  - Instruction Test Registers
    252
- Instruction Test Command Register (ITEST_COMMAND)
  253
- Instruction Test Data 1 Register (ITEST_DATA1)
  254
- Instruction Test Data 0 Register (ITEST_DATA0)
  255
- Example Code for Direct Invalidation
  256
- L1 Data Memory
  263
  - L1 Data SRAM
    264
  - L1 Data Cache
    266
    
    Example of Mapping Cacheable Address Space into Data Banks
    267
    
    Data Cache Access
    271
    
    Cache Write Method
    272
    
    Data Cache Control Instructions
    273
  - Data Test Registers
    273
    
    Data Test Command Register (DTEST_COMMAND)
    275
    
    Data Test Data 1 Register (DTEST_DATA1)
    275
    
    Data Test Data 0 Register (DTEST_DATA0)
    277
  - On-Chip Level 2 (L2) Memory
    278
    
    On-Chip L2 Bank Access
    278
    
    Latency
    279
    
    Off-Chip L2 Memory
    281
  - Memory Protection and Properties
    282
    
    Memory Management Unit
    282
    
    Memory Pages
    284
    
    Page Descriptor Table
    286
    
    CPLB Management
    287
    
    MMU Application
    288
    
    Examples of Protected Memory Regions
    289
    
    DCPLB Data Registers (Dcplb_Datax)
    291
    
    ICPLB Data Registers (Icplb_Datax)
    293
    
    DCPLB Address Registers (Dcplb_Addrx)
    295
    
    ICPLB Address Registers (Icplb_Addrx)
    297
    
    (Dcplb_Fault_Addr, Icplb_Fault-Addr)
    300
    
    DCPLB and ICPLB Fault Address Registers
    300
    
    ICPLB Status Register (ICPLB_STATUS)
    300
    
    Icplb_Status)
    300
    
    DCPLB Fault Address Register (DCPLB_FAULT_ADDR)
    301
  - Memory Transaction Model
    302
    
    ICPLB Fault Address Register (ICPLB_FAULT_ADDR)
    302
  - Load/Store Operation
    303
    
    Interlocked Pipeline
    304
    
    Ordering of Loads and Stores
    305
    
    Synchronizing Instructions
    306
    
    Speculative Load Execution
    307
    
    Conditional Load Behavior
    308
  - Working with Memory
    309
    
    Alignment
    309
    
    Atomic Operations
    309
    
    Memory-Mapped Registers
    310
    
    Core MMR Programming Code Example
    311
Chip Bus Hierarchy

313
- Internal Interfaces
  313
- ADSP-BF535 Internal Clocks
  314
- Core Overview
  315
- System Overview
  317
  - System Bus Interface Unit (SBIU)
    317
  - On-Chip L2 SRAM Memory Interface
    319
- System Interfaces
  319
  - Peripheral Bus (PAB)
    320
    
    PAB Arbitration
    320
    
    PAB Performance
    320
    
    PAB Agents (Masters, Slaves)
    321
  - DMA Bus (DAB)
    322
    
    DAB Arbitration
    322
    
    DAB Performance
    323
    
    DAB Bus Agents (Masters)
    326
  - External Access Bus (EAB)
    326
    
    EAB Arbitration
    327
    
    EAB Performance
    327
    
    EAB Bus Agents (Masters, Slaves)
    329
  - External Mastered Bus (EMB)
    330
    
    EMB Arbitration
    330
    
    EMB Bus Agents (Masters, Slaves, Bridges)
    330
    
    EMB Performance
    330
    
    Resources Accessible from EMB
    331
Dynamic Power Management

333
- Clocking
  333
  - Phase Locked Loop and Clock Control
    334
    
    PLL Overview
    334
  - PLL Clock Multiplier Ratios
    335
    
    Core Clock/System Clock Ratio Control
    337
- PLL Memory-Mapped Registers (Mmrs)
  339
- Dynamic Power Management Controller
  343
  - Operating Modes
    344
    
    Active Mode
    344
    
    Full on Mode
    344
    
    Sleep Mode
    345
    
    Deep Sleep Mode
    346
  - Operating Mode Transitions
    346
    
    PLL Programming Sequence
    349
    
    Programming Operating Mode Transitions
    349
    
    PLL Programming Sequence Continues
    351
    
    Examples
    352
  - Peripheral Clocking
    354
    
    Peripheral Clock Enable Register (PLL_IOCK)
    354
  - Dynamic Supply Voltage Control
    355
    
    Changing Voltage
    356
    
    PCI Power Savings
    356
    
    External Voltage Regulator Example
    357
    
    Power Saving Sequence
    357
    
    High Performance Sequence
    358
Direct Memory Access

361
- Descriptor Based DMA
  363
  - DMA Descriptor Block Structure
    364
  - DMA Configuration Word
    366
  - Setting up Descriptor Based DMA
    368
  - Descriptor-Based DMA Operation
    369
- Autobuffer Based DMA
  375
  - Setting up Autobuffer Based DMA
    375
- DMA Control Registers
  376
- Memory DMA (Memdma)
  391
- Memdma Control Registers
  392
  - Destination Memory DMA Configuration Register (MDD_DCFG)
    393
  - Destination Memory DMA Transfer Count Register (MDD_DCT)
    394
- Destination Memory DMA Next Descriptor Pointer
  396
  - Register (MDD_DND)
    397
- Destination Memory DMA Current Descriptor Pointer
  397
  - Register (MDD_DCP)
    398
- Destination Memory DMA Interrupt Register (MDD_DI)
  398
- Source Memory DMA Configuration Register
  399
  - (Mds_Dcfg)
    399
- Source Memory DMA Transfer Count Register
  400
  - (Mdd_Dct)
    400
- Source Memory DMA Start Address Registers
  401
- Source Memory DMA Interrupt Register (MDS_DI)
  403
- Performance/Throughput for Memdma
  404
- DMA Abort Conditions
  404
- DMA Bus Error Conditions
  405
  - Data Misalignment
    406
  - Illegal Memory Access
    406
Spi Compatible Port Controllers

407
- Interface Signals
  410
- SPI Registers
  413
- SPI Transfer Formats
  434
- SPI General Operation
  436
  - Clock Signals
    437
  - Master Mode Operation
    438
  - Transfer Initiation from Master (Transfer Modes)
    439
    
    Slave Mode Operation
    440
    
    Slave Ready for a Transfer
    441
- Error Signals and Flags
  441
  - Mode Fault Error (MODF)
    442
  - Transmission Error (TXE)
    443
  - Reception Error (RBSY)
    443
  - Transmit Collision Error (TXCOL)
    443
- Beginning and Ending an SPI Transfer
  444
11 Serial Port Controllers

447
12 Uart Port Controller

523
- Serial Communications
  524
- Uartx Control and Status Registers
  524
- Non-DMA Mode
  537
  - Uartx Scratch Registers (Uartx_Scr)
    537
- DMA Mode
  539
- Mixing Modes
  539
- UART DMA Receive Registers
  540
- UART DMA Transmit Registers
  549
- Irda Support
  557
13 Pci Bus Interface

563
- PCI Specification
  564
- PCI Device Function
  565
- PCI Host Function
  565
- Processor Core Access to PCI Space
  565
- External PCI Requirements
  566
- Device Mode Operation
  566
  - Outbound Transactions (ADSP-BF535 Processor as PCI Initiator)
    568
    
    General Outbound Operation
    568
    
    Outbound Error Detection and Reporting
    569
    
    Supported Transactions to PCI
    570
  - Inbound Transactions
    572
    
    General Inbound Operation
    572
    
    Target
    572
    
    Inbound Error Detection and Reporting
    574
    
    Supported Transactions from PCI
    574
    
    Unsupported Transactions from PCI
    574
- Host Mode Operation
  575
  - Outbound Transactions (ADSP-BF535 Processor as PCI Initiator)
    575
  - Inbound Transactions
    576
- Outbound Configuration Transactions
  577
- Reset Behavior and Control
  578
- Interrupt Behavior and Control
  579
- PCI Programming Model
  580
  - Bus Operation Ordering
    580
- System MMR Control and Status Registers
  581
  - PCI Bridge Control Register (PCI_CTL)
    582
  - PCI Status Register (PCI_STAT)
    583
  - PCI Interrupt Controller Register (PCI_ICTL)
    584
  - PCI Outbound Memory Base Address Register
    585
    
    (Pci_Mbap)
    585
  - PCI Outbound I/O Configuration Address Register
    586
    
    (Pci_Cbap)
    586
  - PCI Inbound Memory Base Address Register
    587
    
    (Pci_Tmbap)
    587
  - PCI Inbound I/O Base Address Register (PCI_TIBAP)
    587
- Configuration Space Control and Status Registers
  588
  - PCI Device Memory BAR Mask Register
    588
    
    (Pci_Dmbarm)
    588
  - PCI Device I/O BAR Mask Register (PCI_DIBARM)
    589
- PCI Configuration Device ID Register (PCI_CFG_DIC)
  591
- PCI Configuration Vendor ID Register (PCI_CFG_VIC)
  592
- PCI Configuration Status Register (PCI_CFG_STAT)
  593
- PCI Configuration Command Register (PCI_CFG_CMD)
  594
- PCI Configuration Class Code Register (PCI_CFG_CC)
  595
- PCI Configuration Revision ID Register (PCI_CFG_RID)
  596
- PCI Configuration bist Register (PCI_CFG_BIST)
  597
- PCI Configuration Header Type Register (PCI_CFG_HT)
  598
- PCI Configuration Memory Latency Timer Register
  598
  - (Pci_Cfg_Mlt)
    598
- PCI Configuration Cache Line Size Register
  599
  - (Pci_Cfg_Cls)
    599
- PCI Configuration Memory Base Address Register
  600
  - (Pci_Cfg_Mbar)
    600
- PCI Configuration I/O Base Address Register
  601
  - (Pci_Cfg_Ibar)
    601
- PCI Configuration Subsystem ID Register
  602
  - (Pci_Cfg_Sid)
    602
- PCI Configuration Subsystem Vendor ID Register
  602
  - (Pci_Cfg_Svid)
    602
- PCI Configuration Maximum Latency Register
  603
  - (Pci_Cfg_Maxl)
    603
- PCI Configuration Minimum Grant Register
  604
  - (Pci_Cfg_Ming)
    604
- PCI Configuration Interrupt Pin Register (PCI_CFG_IP)
  604
- PCI Configuration Interrupt Line Register (PCI_CFG_IL)
  605
  - PCI I/O Issues
    606
    
    Reflected Wave Switching
    606
    
    PCI Clock Requirements
    607
    
    Power Sequencing
    607
    
    14 Usb Device
    609
  - Convention
    609
  - Requirements
    610
    
    USB Requirements
    611
    
    Data Flow and Traffic Scheduling
    612
    
    USB Implementation
    612
  - Block Diagram
    614
    
    UDC Block
    614
    
    Clock Control Block
    615
    
    Front-End Interface Block
    615
    
    Transaction Decode and Clock Synchronization Block
    615
    
    Memory Interface Block
    616
    
    Registers and Control Block
    616
    
    DMA Master Block
    617
    
    PAB Interface Block
    618
  - Features and Modes
    618
    
    Endpoint Types
    618
  - Data Transfers
    619
    
    Control Transfers
    619
  - UDC Configuration Control
    620
  - Suspend Operation
    621
  - Clocking
    621
  - USB Transceiver
    621
- Registers
  622
Usb Device

623
- USBD Module Configuration and Control Register
  629
  - (Usbd_Ctrl)
    629
- Global Interrupt Register (USBD_GINTR)
  631
- DMA Master Channel Configuration Register
  632
  - (Usbd_Dmacfg)
    632
- Global Interrupt Mask Register (USBD_GMASK)
  632
- DMA Master Channel Base Address Low Register
  633
- Interrupt Descriptions
  645
  - USB General Interrupts
    646
    
    USBD_MSOF - Missed Start of Frame
    647
    
    USBD_RESUME - Resume Signaling
    647
    
    USBD_RST - Reset Signaling Detected
    647
    
    USBD_SUSP - Device Suspended
    647
    
    USBD_FRMAT – Frame Match
    648
  - Dma_Comp
    649
- USB Endpoint Interrupts
  650
  - USBD_BCSTAT – Buffer Complete
    651
- USB Programming Model
  652
  - USBD Device Initialization
    654
  - USB Data Transfers
    655
    
    How to Transfer Data
    656
    
    Bulk Transfers
    657
    
    Bulk out
    659
    
    Isochronous Transfers
    661
    
    Control Transfers
    664
    
    Control Transfer, no Data Phase
    665
    
    Control Transfer with Data Phase
    666
    
    Control Transfers Gone Bad
    667
    
    Endpoint Errors
    668
    
    Exception Handling
    668
    
    Isochronous Transfers Error Detection
    669
    
    Reset Signaling Detected on USB
    669
  - References
    670
    
    Suspend/Resume Considerations
    670
15 Programmable Flags

673
- Programmable Flag Memory-Mapped Registers (Mmrs)
  674
- Performance/Throughput
  683
Timers

685
- General-Purpose Timers
  685
- General-Purpose Timer Registers
  686
- Timer Modes
  697
- Watchdog Timer
  709
  - Watchdog Count Register (WDOG_CNT)
    710
    
    Watchdog Control Register (WDOG_CTL)
    711
  - RTC Programming Model
    714
    
    Interrupts
    719
    
    RTC Interrupt Control Register (RTC_ICTL)
    720
    
    RTC Interrupt Status Register (RTC_ISTAT)
    721
    
    RTC Stopwatch Count Register (RTC_SWCNT)
    722
    
    RTC Alarm Register (RTC_ALARM)
    723
    
    RTC Enable Register (RTC_FAST)
    724
    
    Block Diagram
    727
  - Internal Memory Interfaces
    728
  - EBIU Arbitration
    729
  - EBIU Programming Model
    731
    
    Error Detection
    732
  - Asynchronous Memory Interface
    733
    
    Asynchronous Memory Address Decode
    734
    
    ARDY Input Control
    737
  - Programmable Timing Characteristics
    740
    
    Asynchronous Writes
    742
    
    Asynchronous Writes Followed by Reads
    745
    
    Asynchronous Accesses by Memdma
    747
    
    Asynchronous Reads
    748
    
    Asynchronous Writes
    750
Real-Time Clock (Rtc)

714
- SDRAM Controller (SDC)
  752
- SDRAM Control Status Register (EBIU_SDSTAT)
  777
- SDRAM Refresh Rate Control Register (EBIU_SDRRC)
  778
- SDRAM External Bank Address Decode
  780
- SDRAM Address Mapping
  783
  - Bit Wide SDRAM Address Muxing
    784
  - Bit Wide SDRAM Address Muxing
    789
- Data Mask (SDQM[3:0]) Encodings
  791
- Sdram Banks
  793
- SDC Operation
  794
- Read Buffer (Prefetch) Operation
  796
- SDC Commands
  799
  - Precharge Command
    800
  - Bank Activate Command
    801
  - Read/Write Command
    802
  - Self-Refresh Command
    803
  - No Operation/Command Inhibit Commands
    804
- SDRAM Performance
  805
System Design

813
- Pin Descriptions
  813
- Resetting the Processor
  814
  - Managing Core and System Clocks
    815
- Configuring and Servicing Interrupts
  817
- Semaphores
  818
  - Example Code for Query Semaphore
    819
- Data Delays, Latencies and Throughput
  820
- External Memory Design Issues
  821
  - Avoiding Bus Contention
    822
  - Supported SDRAM Configurations
    823
  - Example SDRAM Interfaces
    824
- High Frequency Design Considerations
  826
  - Signal Integrity
    827
    
    Decoupling Capacitors and Ground Planes
    828
    
    Recommended Reading
    829
  - Watchpoint Unit
    831
    
    Instruction Watchpoints
    834
    
    Watchpoint Instruction Address Registers (Wpiax)
    835
    
    Data Address Watchpoints
    840
    
    Watchpoint Data Address Registers (Wpdax)
    841
    
    Watchpoint Status Register (WPSTAT)
    844
    
    Trace Buffer Control Register (TBUFCTL)
    846
    
    Trace Buffer Status Register (TBUFSTAT)
    847
    
    Trace Buffer Register (TBUF)
    848
Blackfin Processor's Debug

831
- Performance Monitoring Unit
  849
  - Performance Monitor Counter Registers (Pfcntrx)
    850
  - Event Monitor Table
    852
- Cycle Counter
  854
- Product Identification Registers
  855
Blackfin Processor Core Mmr Assignments

861
- L1 Data Memory Controller Registers
  861
- L1 Instruction Memory Controller Registers
  864
- Interrupt Controller Registers
  867
- Core Timer Registers
  869
- Trace Unit Registers
  870
- Performance Monitor Registers
  872
System Mmr Assignments

874
- Clock and System Control Registers
  874
- System Interrupt Controller Registers
  875
- Watchdog Timer Registers
  876
- UART0 Controller Registers
  877
- UART1 Controller Registers
  880
- Timer Registers
  883
- Programmable Flag Registers
  885
- SPORT0 Controller Registers
  886
- SPORT1 Controller Registers
  891
- SPI0 Controller Registers
  895
- SPI1 Controller Registers
  897
- Memory DMA Controller Registers
  898
  - Asynchronous Memory Controller—Ebiu
    900
  - USB Device Registers
    903
- System DMA Control Registers
  907
Test Features

909
- Boundary-Scan Architecture
  910
  - Instruction Register
    912
  - Public Instructions
    914
    
    IDCODE – Binary Code 00010
    915
  - Boundary-Scan Register
    916
Numeric Formats

935
- Unsigned or Signed: Two's-Complement Format
  935
- Binary Multiplication
  938
  - Fractional Mode and Integer Mode
    939
- Block Floating-Point Format
  940

Advertisement

Advertisement

Related Products

Analog Devices Categories

Motherboard Computer Hardware Media Converter Extender Controller

More Analog Devices Manuals