Analog Devices ADSP-SC58 Series Hardware Reference Manual page 821

ADSP-SC58x UART Register Descriptions
Table 17-12: UART_IMSK Register Fields (Continued)
Bit No.
(Access)
7 EAWI
(R/W)
6 ERFCI
(R/W)
5 ETFI
(R/W)
4 EDTPTI
(R/W)
17–34
Bit Name
Enable Address Word Interrupt Mask Status.
If set (interrupt unmasked), the UART_IMSK.EAWI bit indicates generation of a sta-
tus interrupt request when an Address word in MDB-mode is present in the
UART_RBR. A received word is an address word if the UART_STAT.ADDR bit is set.
Enable Receive FIFO Count Interrupt Mask Status.
If set (interrupt unmasked), the UART_IMSK.ERFCI bit indicates enabling of the
receive buffer threshold interrupt request if signaled by the UART_STAT.RFCS bit.
Read the
Enable Transmission Finished Interrupt Mask Status.
If set (interrupt unmasked) the UART_IMSK.ETFI bit indicates enabling of inter-
rupt generation on the status interrupt channel when the transmit buffer register, the
transmit address register, and the transmit shift register are all empty as indicated by
the UART_STAT.TFI. The UART_IMSK.ETFI interrupt can be used to avoid ex-
pensive polling of the UART_STAT.TEMT bit, when the UART clock or line drivers
should be disabled after transmission has completed. W1C the UART_STAT.TFI bit
to clear the interrupt request. In DMA operation, the UART_IMSK.ETFI bits func-
tionality might be preferred.
Enable DMA TX Peripheral Triggered Interrupt Mask Status.
If set (interrupt unmasked), the UART_IMSK.EDTPTI bit indicates enabling of the
DMA completion interrupt request to be delayed until the data has left the UART
completely. This bit is required for DMA transmit operation only. If set, the UART
can generate a DMA interrupt request by the time the UART_STAT.TEMT bit goes
high after the last DMA data word is transmitted.
When UART_IMSK.EDTPTI is set, usually the DMA_CFG.INT field is cleared to
00 in a STOP mode DMA. This set up suppresses the normal completion interrupt
request, and the UART_STAT.TEMT event is signaled through the DMA controller
and triggers the DMA interrupt. If both (DMA_CFG.INT not 00 and
UART_IMSK.EDTPTI set), two interrupts are requested at the end of a STOP mode
DMA.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Interrupt is masked
1 Interrupt is unmasked
register sufficient times to clear the interrupt request.
UART_RBR
0 Interrupt is masked
1 Interrupt is unmasked
0 Interrupt is masked
1 Interrupt is unmasked
0 Interrupt is masked
1 Interrupt is unmasked