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Data Integrity
Syndrome: 0x07,
0x70, 0x73, 0x75, 0x76,
0x79, 0x7A, 0x7C, 0x7F
Syndrome:
0x07, 0x1F, 0x2F, 0x37,
0x4F, 0x57, 0x67, 0x7F
Syndrome:
0x68, 0x6E, 0x6D, 0x6B,
0x79, 0x7A, 0x7C, 0x7F
Syndrome: 0x3B, 0x5B,
0x3D, 0x3E, 0x5D, 0x5E,
0x7F, 0x79, 0x7A, 0x7F
Figure 9-4: Hsiao Error Reports
The XOR gate detects single-bit errors and does not flag any dual-bit error. But, the gate does flag 50% of the other
multi-bit errors undesirably. Extra logic is implemented to increase the detection rate of multi-bit errors to 68.7% as
shown in the figure.
If a single-bit error is detected, the failing bit can be localized and corrected. If all three syndrome bits corresponding
to a specific data bit are 1, a data error is assumed. The respective data bit is toggled on its way to the system bus.
ECC Hardware Control
After reset, ECC protection is enabled. The boot code initializes all L2 SRAM data and checksum cells. ECC pro-
tection adds some cycle penalty when 8-bit and 16-bit values write L2 memory. Disable ECC protection for individ-
ual SRAM banks by setting the L2CTL_CTL.BK0EDIS through L2CTL_CTL.BK7EDIS disable bits. Due to
caching mechanisms of the processor cores and data bursting of the DMA channels, 8-bit and 16-bit write accesses
are rather uncommon. Typically, only two-dimensional DMA operations or uncached 8-bit and 16-bit store instruc-
tion can trigger these writes.
For system integrity testing, the L2 system memory also provides a method for accessing the ECC checksum area
directly. The L2CTL_CTL.ECCMAP0 through L2CTL_CTL.ECCMAP7 bits map the ECC checksum values into
the address space of the data bits. This feature can be activated per SRAM bank. In this mode, only 32-bit accesses
are allowed. 32-bit reads return the checksum value in the lower 7 bits while the upper bits read zero. Any 32-bit
write overwrites the checksum. The upper bits are ignored.
Using this checksum mapping feature, safety critical applications can verify the ECC hardware during boot up se-
quence or even at run time. It is not required to set the L2CTL_CTL.BK0EDIS through
L2CTL_CTL.BK7EDIS disable bits explicitly. To test the ECC hardware, use the following steps:
1. Write data values to L2 SRAM destination (preferable an even number of 32-bit words).
2. If data cache enabled, make sure that it flushes out data.
9–8
Syndrome
6
5
4
3
2
1
0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Syndromes not equal 0x00
Syndromes having
an odd number of 1's
Multi-bit error
>1-bit error
Uncorrectable
error
One bit error
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