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DMC Programming Model
1. Perform first-time DMC initialization, as needed.
ADDITIONAL INFORMATION: Perform this step only for the first time DMC initialization after power-up
or reset. Skip this step if reinitializing the DMC.
a. Set the DMC_PHY_CTL0.RESETDLL bit of the
b. Initialize the CGU to change the DCLK frequency.
a. Clear the DMC_PHY_CTL0.RESETDLL bit of the
2. Reinitialize the DMC with a DCLK change
a. Place the DMC in self-refresh mode.
b. Set the DMC_PHY_CTL0.RESETDLL bit of the
c. Initialize the CGU to change the DCLK frequency.
d. Clear the DMC_PHY_CTL0.RESETDLL bit of the
e. Bring the DMC out of self-refresh mode.
3. If not already done, wait 9000 DCLK cycles to ensure that the DLL locked.
4. Program the DMC_CFG, DMC_CTL, DMC_TR0, DMC_TR1, and
to set proper SDRAM cycle timing options.
ADDITIONAL INFORMATION: For example, t
5. Program the shadow registers
DMC_EMR1 (DDR2)/DMC_EMR1
cy, additive latency, and other parameters.
6. Finally, after programming these registers, write the DMC_CTL.INIT bit to the DMC control register to be-
gin the power-up initialization sequence.
7. Wait for the SDRAM initialization sequence to complete by making sure that the DMC_STAT.INITDONE
bit is set.
10–20
, t
RAS
(DDR2/DDR3/LPDDR),
DMC_MR
(LPDDR)
DMC_EMR1
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMC_PHY_CTL0
register.
DMC_PHY_CTL0
register.
DMC_PHY_CTL0
register.
DMC_PHY_CTL0
register.
DMC_TR2
registers to the appropriate values
, t
, t
, t
, t
RC
RP
RCD
WR
FAW
DMC_EMR1
(DDR3), with the needed burst length, CAS laten-
are some of the parameters.
(DDR2)/DMC_EMR1(DDR3),
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