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L2 System Memory Functional Description
The following sections provide a functional description of the L2 system memory.
ADSP-SC58x L2CTL Interrupt List
Table 9-1: ADSP-SC58x L2CTL Interrupt List
Interrupt
Name
ID
8
L2CTL0_ECC_ERR
ADSP-SC58x L2CTL Register List
The L2 memory controller (L2CTL) includes the controls to manage each L2 memory bank independently. A set of
registers governs L2CTL operations. For more information on L2CTL functionality, see the L2CTL register descrip-
tions.
Table 9-2: ADSP-SC58x L2CTL Register List
Name
L2CTL_CTL
L2CTL_EADDR0
L2CTL_EADDR1
L2CTL_ERRADDR0
L2CTL_ERRADDR1
L2CTL_ERRADDR2
L2CTL_ERRADDR3
L2CTL_ERRADDR4
L2CTL_ERRADDR5
L2CTL_ERRADDR6
L2CTL_ERRADDR7
L2CTL_ET0
L2CTL_ET1
L2CTL_RFA
L2CTL_RPCR
L2CTL_STAT
L2CTL_WPCR
L2 System Memory Block Diagram
The ADSP-SC58x Complete L2 System Block Diagram figure shows the complete L2 system memory, including the
three memory block instances: L2CTL0, L2CTL1, and L2CTL2. The L2CTL0 block contains boot ROM code for
9–2
Description
L2CTL0 ECC Error
Description
Control Register
Error Type 0 Address Register
Error Type 1 Address Register
ECC Error Address 0 Register
ECC Error Address 1 Register
ECC Error Address 2 Register
ECC Error Address 3 Register
ECC Error Address 4 Register
ECC Error Address 5 Register
ECC Error Address 6 Register
ECC Error Address 7 Register
Error Type 0 Register
Error Type 1 Register
Refresh Address Register
Read Priority Count Register
Status Register
Write Priority Count Register
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Sensitivity
DMA
Channel
Level
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