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LP Event Control
can read the
LP_STAT
writing one to the bit resets the bit and disables the corresponding interrupt.
Status and Error Signals
This section explains the various status signals in the
• Transfer Status signals. The link port uses the bus status bit (LP_STAT.LPBS) to give the status of the bus
condition (busy or idle), when the link port is configured as transmitter. The LP_STAT.LPBS is high if the
link port drives data into the link port pins. Programs can poll this bit after polling the LP_STAT.FFST bit
to disable the link port safely.
The link buffer status (LP_STAT.FFST) field directly indicates the status of the FIFO (including empty or
full conditions) during data transfer. Software can poll this field in the
FIFO (in case of transmission) or reading from the FIFO (in case of reception). The LP_STAT.FFST bit is
automatically cleared when the link port is disabled.
• Transfer Request Status signals. The link port uses the receive request status (LP_STAT.LRRQ) bit to indicate
that an external receiver wants to receive data (in case the link port is a disabled transmitter). The link port uses
the transmit request status (LP_STAT.LTRQ) bit to indicate that an external transmitter wants to send data
(in case the link port is a disabled receiver). Software can poll these bits to enable the transmitter or receiver
accordingly.
• Error Status signals. In receive mode 32-bit data is received in four chunks of 8-bit data. This data is then
packed to a single 32-bit data before loading the FIFO. The link buffer error status (LP_STAT.LPACK) bit is
high during this packing process and goes low after packing.
The link port overflow status (LP_STAT.ROVF) bit is set when the receive FIFO overflows. This event can
occur if the transmitter continues to transmit data even though the receiver has deasserted LP_ACK causing
the receiver FIFO to overflow.
LP Programming Model
The following sections provide information on configuring the operating mode and enabling the link ports.
•
Setting Up a DMA Transmit Operation
•
Setting Up a DMA Receive Operation
•
Setting Up a Core Transmit Operation
•
Setting Up a Core Receive Operation
Setting Up a DMA Transmit Operation
This following procedure describes the typical steps for configuring the link ports in DMA transmit mode.
1. Enable the link port pins in the GPIO port mux using the appropriate
15–14
register bits to determine the type of interrupt. These bits are write-one-to-clear (W1C);
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register.
LP_STAT
LP_STAT
PORT_FER
register before writing to the
and
PORT_MUX
registers.
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