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GIC Functional Description
GIC Block Diagram
The GIC Block Diagram shows the event management architecture.
Figure 7-30: GIC Block Diagram
ADSP-SC58x GICDST Register List
GIC Distributor Port
Table 7-29: ADSP-SC58x GICDST Register List
Name
GICDST_EN
GICDST_SGI_PRIO[n]
GICDST_SPI_PRIO[n]
GICDST_SGI_ACTIVE
GICDST_SGI_CTL
GICDST_SGI_PND_CLR
GICDST_SGI_PND_SET
GICDST_SGI_SECURITY
GICDST_SPI[n]
GICDST_SPI_ACTIVE[n]
GICDST_SPI_CFG[n]
GICDST_SPI_EN_CLR[n]
GICDST_SPI_EN_SET[n]
GICDST_SPI_PND_CLR[n]
GICDST_SPI_PND_SET[n]
GICDST_SPI_SECURITY[n]
GICDST_SPI_TRGT[n]
ADSP-SC58x GICCPU Register List
GIC CPU Port
7–60
SYSTEM
Distributer
INTERRUPTS
Port 0
Description
GIC Port 0 Enable
Software Generated Interrupt Priority Register
Shared Peripheral Interrupt Priority Register
Software Generated Interrupt Active Register
Software Generated Interrupt Control Register
Software Generated Interrupt Clear-Pending Register
Software Generated Interrupt Pending Set Register
Software Generated Interrupt Security Register
Shared Peripheral Interrupt Register
Shared Peripheral Interrupt Active Register
Shared Peripheral Interrupt Configuration Register
Shared Peripheral Interrupt Enable Clear Register
Shared Peripheral Interrupt Enable Set Register
Shared Peripheral Interrupt Pending Clear Register
Shared Peripheral Interrupt Pending Set Register
Shared Peripheral Interrupt Security Register
Shared Peripheral Interrupt Processor Targets Register
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
GIC
CPU
CORTEX A5
Port 1
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