Analog Devices ADSP-SC58 Series Hardware Reference Manual page 33

ADSP-SC58x TIMER Register Descriptions ............................................................................................ 20–25
Broadcast Delay Register ....................................................................................................................... 20–26
Broadcast Period Register ...................................................................................................................... 20–27
Broadcast Width Register ...................................................................................................................... 20–28
Data Interrupt Latch Register ................................................................................................................ 20–29
Data Interrupt Mask Register ................................................................................................................ 20–30
Error Type Status Register ..................................................................................................................... 20–31
Run Register .......................................................................................................................................... 20–33
Run Clear Register ................................................................................................................................ 20–34
Run Set Register .................................................................................................................................... 20–35
Status Interrupt Latch Register .............................................................................................................. 20–36
Status Interrupt Mask Register .............................................................................................................. 20–37
Stop Configuration Register .................................................................................................................. 20–38
Stop Configuration Clear Register ......................................................................................................... 20–39
Stop Configuration Set Register ............................................................................................................ 20–40
Timer n Configuration Register ............................................................................................................ 20–41
Timer n Counter Register ...................................................................................................................... 20–45
Timer n Delay Register .......................................................................................................................... 20–46
Timer n Period Register ......................................................................................................................... 20–47
Timer n Width Register ......................................................................................................................... 20–48
Trigger Slave Enable Register ................................................................................................................. 20–49
Trigger Master Mask Register ................................................................................................................ 20–50
Watchdog Timer (WDOG)
WDOG Features.......................................................................................................................................... 21–1
WDOG Functional Description .................................................................................................................. 21–2
ADSP-SC58x WDOG Register List ......................................................................................................... 21–3
ADSP-SC58x WDOG Interrupt List ...................................................................................................... 21–3
WDOG Block Diagram............................................................................................................................ 21–3
Internal Interface ..................................................................................................................................... 21–3
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference xxxiii