Analog Devices ADSP-SC58 Series Hardware Reference Manual page 711

Sharc+ processor
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Table 16-4: ADSP-SC58x SPI Trigger List Slaves (Continued)
Trigger ID
Name
38
SPI2_RXDMA
ADSP-SC58x SPI DMA Channel List
Table 16-5: ADSP-SC58x SPI DMA Channel List
DMA ID
DMA22
DMA23
DMA24
DMA25
DMA26
DMA27
SPI Block Diagram
The SPI Controller Block Diagram illustrates the blocks of the SPI module. The module is comprised of three pri-
mary parts:
• SPI core contains the receive and transmit FIFOs and their associated shift registers
• Control blocks contain the synchronizer and logic to control the data flow through the data pipelines
• Register block
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
SPI2 RX DMA Channel
DMA Channel Name
SPI0_TXDMA
SPI0_RXDMA
SPI1_TXDMA
SPI1_RXDMA
SPI2_TXDMA
SPI2_RXDMA
SPI Functional Description
Sensitivity
Pulse
Description
SPI0 TX DMA Channel
SPI0 RX DMA Channel
SPI1 TX DMA Channel
SPI1 RX DMA Channel
SPI2 TX DMA Channel
SPI2 RX DMA Channel
16–5

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