Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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ADSP-214xx SHARC

Processor

Hardware Reference

Includes ADSP-2146x, ADSP-2147x,

ADSP-2148x Product Families

Revision 0.3, July 27, 2010

Part Number

82-000469-01

Analog Devices, Inc.

One Technology Way

Norwood, Mass. 02062-9106

www.BDTIC.com/ADI

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Summary of Contents for Analog Devices SHARC ADSP-214 Series

Page 1 ADSP-214xx SHARC Processor ® Hardware Reference Includes ADSP-2146x, ADSP-2147x, ADSP-2148x Product Families Revision 0.3, July 27, 2010 Part Number 82-000469-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 www.BDTIC.com/ADI...
Page 2 Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use;...
Page 3: Table Of Contents
Registration for MyAnalog.com ..........lxvi EngineerZone ............... lxvii Social Networking Web Sites ..........lxvii Supported Processors ..............lxvii Product Information ..............lxviii Analog Devices Web Site ............. lxviii VisualDSP++ Online Documentation ......... lxviii Technical Library CD ............lxix Notation Conventions ..............lxx INTRODUCTION Design Advantages ................
Page 4 Contents SHARC Family Product Offerings ........... 1-2 Processor Architectural Overview ..........1-2 Processor Core ................ 1-2 I/O Peripherals ............... 1-3 I/O Processor ..............1-3 Digital Audio Interface (DAI) ..........1-3 Interrupt Controller ............1-4 Signal Routing Unit ............1-4 Digital Peripheral Interface (DPI) ........1-4 Interrupt Controller ............
Page 5 Contents Serial Port TCB ..............2-14 SPI TCB ................2-14 UART TCB ................2-15 Link Port TCB ..............2-15 FIR Accelerator TCB ............. 2-16 IIR Accelerator TCB .............. 2-17 FFT Accelerator TCB ............2-18 External Port TCB ..............2-19 Clocking ..................2-22 Functional Description ...............
Page 6 Contents TCB Memory Storage ............2-32 Chain Assignment ............2-33 Starting Chain Loading ............ 2-34 TCB Chain Loading Priority ..........2-35 Chain Insert Mode (SPORTs Only) ........2-36 Fixed DMA Channel Arbitration ........... 2-36 Peripheral DMA Bus ............2-42 External Port DMA Bus ............ 2-43 SPORT/External Port DMA Bus ........
Page 7 Contents IOP Effect Latency ..............2-49 IOP Throughput ..............2-50 Programming Model ..............2-50 General Procedure for Configuring DMA ......2-51 EXTERNAL PORT Features ..................3-2 Pin Descriptions ................3-3 Pin Multiplexing ..............3-3 Register Overview ................. 3-3 Clocking AMI/SDRAM ..............3-5 Clocking AMI/DDR2 ..............
Page 8 Contents Data Packing ..............3-15 External Access Extension ..........3-15 Predictive Reads ............... 3-16 SDRAM Controller (ADSP-2147x/ADSP-2148x) ........... 3-17 Features ................3-17 Functional Description ............3-18 SDRAM Commands ............3-20 Load Mode Register ............3-20 Bank Activation ............3-21 Single Precharge ............3-21 Precharge All ..............
Page 9 Contents Timing Parameters ............3-37 Fixed Timing Parameters ..........3-37 Data Mask ................ 3-38 Resetting the Controller ............ 3-38 Operating Modes ..............3-38 Parallel Connection of SDRAMs ........3-38 Buffering Controller for Multiple SDRAMs ....3-39 SDRAM Read Optimization ..........3-40 Core Accesses ..............
Page 10 Contents Load Extended Mode Register 3 ........3-53 Bank Activation ............3-53 Precharge ..............3-54 Precharge All ..............3-54 Burst Read ..............3-54 Burst Write ..............3-55 Auto-Refresh ..............3-56 Self-Refresh Entry ............3-57 Self-Refresh Exit ............3-57 Precharge Power-Down Entry ........3-58 Precharge Power-down Exit ...........
Page 11 Contents Initialization Time ............3-70 Internal DDR2 Bank Access ..........3-71 Single Bank Access ............3-71 Multibank Access ............3-71 Force Activation Window ..........3-72 Multi Bank Operation with Data Packing ..... 3-73 Fixed Timing Parameters ..........3-74 Operating Modes ..............3-75 Parallel Connection of DDR2s ..........
Page 12 Contents Conditional Instructions ........... 3-86 SIMD Access ................ 3-86 SDRAM ................3-86 DDR2 ................3-87 External Instruction Fetch ..........3-88 Interrupt Vector Table (IVT) ........3-88 Fetching ISA Instructions From External Memory ..3-89 Instruction Packing ............3-90 16-Bit Instruction Storage and Packing ......3-90 8-Bit Instruction Storage and Packing ......
Page 13 Contents External Address Calculation ........... 3-106 Delay Line DMA ..............3-111 External Address Calculation for Reads ......3-112 Interrupts ................3-114 Access Completion ............3-115 Internal Transfer Completion .......... 3-115 Interrupt Dependency on DMA Mode ......3-115 External Port Throughput ............3-116 AMI Data Throughput ............
Page 14 Contents Additional Information ........... 3-124 AMI Initialization ............3-125 SDRAM Controller ............. 3-126 Power-Up Sequence ............3-126 Output Clock Generator Programming Model ....3-127 Self-Refresh Mode ............3-127 Changing the VCO Clock During Runtime ....3-128 DDR2 Controller ............... 3-129 Power-Up Sequence ............
Page 15 Contents Multi-Master Conflicts ............4-10 Example Token Passing ............4-11 Data Transfer ................4-13 Link Buffers ................4-13 Transmit Buffer ..............4-14 Receive Buffer ..............4-14 Buffer Status ..............4-15 Core Transfers ............... 4-15 DMA Transfers ..............4-16 Interrupts ................... 4-16 Interrupt Sources ..............
Page 16 Contents Programming Model ..............4-22 Changing the Link Port Clock ..........4-23 Receive DMA ............... 4-24 Transmit DMA ..............4-24 MEMORY-TO-MEMORY PORT DMA Features ..................5-2 Register Overview ................. 5-2 Clocking ..................5-2 Functional Description ..............5-3 Data Transfer Types ..............5-3 Data Buffer ................
Page 17 Contents Functional Description ............6-5 Compute Block ..............6-5 Data Memory ..............6-6 Coefficient Memory ............6-6 Accelerator States ..............6-6 Reset State ..............6-6 Idle State ................ 6-7 Read State ............... 6-7 Processing State ............... 6-7 Write State ..............6-7 Internal Memory Storage .............
Page 18 Contents Data Transfer ................ 6-15 FFT Buffers ..............6-15 DMA Transfers ..............6-15 DMA Channels and TCB Structure ......6-16 Chained DMA .............. 6-16 Interrupts ................6-17 Interrupt Sources ............. 6-18 Servicing DMA Interrupts ..........6-18 Servicing MAC Status Interrupts ........6-18 FFT Performance ..............
Page 19 Contents N >= 512, No Repeat ............6-24 Configure the FFT Control Register ......6-24 Vertical FFT Configuration ........... 6-25 Special Buffer Configuration ......... 6-25 Horizontal FFT Configuration ........6-26 N >= 512, Repeat ............. 6-26 Debug Mode ..............6-27 Write to Local Memory ..........
Page 20 Contents Single Iteration ............. 6-37 Multi-Iteration ............. 6-37 Window Processing ............6-38 Multi Rate Processing ............6-38 Decimation ..............6-38 Interpolation ..............6-39 Channel Processing ............6-40 Floating-Point Data Format ..........6-42 Fixed-Point Data Format ..........6-42 Data Transfer ................ 6-42 DMA Access ..............
Page 21 Contents Single Channel Processing ..........6-48 Multichannel Processing ............ 6-49 Debug Mode ..............6-52 Write to Local Memory ..........6-52 Read from Local Memory ..........6-52 Single Step Mode .............. 6-53 FIR Programming Example ..........6-53 IIR Accelerator ................6-55 Features .................
Page 22 Contents Interrupt Sources .............. 6-64 Debug Features ..............6-65 Local Memory Access ............6-65 Single Step Mode .............. 6-66 Emulation Considerations ..........6-66 Effect Latency ............... 6-66 Write Effect Latency ............6-67 IIR Accelerator Effect Latency ........... 6-67 IIR Throughput ..............6-67 Programming Model .............
Page 23 Contents Duty Cycles ................ 7-7 Dead Time ............... 7-12 Output Control Unit ............. 7-13 Output Enable ..............7-13 Output Polarity ..............7-13 Complementary Outputs ..........7-14 Crossover ................7-14 Emergency Dead Time for Over Modulation ......7-15 Output Control Feature Precedence ........7-17 Operation Modes ................
Page 24 Contents PWM Effect Latency ............. 7-27 MEDIA LOCAL BUS Features ..................8-3 Pin Descriptions ................8-3 Register Overview ................. 8-4 Device Configuration and Status Registers ....... 8-4 Channel Configuration Registers ..........8-4 Clocking ..................8-5 Functional Description ..............8-5 Operating Modes ................8-7 Streaming Channel Frame Synchronization ......
Page 25 Contents I/O Interrupt Mode ............... 8-16 DMA Modes ................. 8-17 DIGITAL APPLICATION/DIGITAL PERIPHERAL INTERFACES Features ..................9-2 Register Overview ................. 9-3 Clocking ..................9-4 Functional Description ..............9-4 DAI/DPI Signal Naming Conventions ........9-7 I/O Pin Buffers ............... 9-7 Pin Buffers as Signal Output ..........9-8 Pin Buffers as Signal Input ..........
Page 26 Contents DAI Routing Capabilities ..........9-24 DPI Routing Capabilities ..........9-25 Pin Buffer Input ............9-26 Pin Buffer Enable ............9-26 Miscellaneous Signals ............ 9-27 DAI Default Routing ..............9-28 DPI Default Routing ..............9-31 Interrupts ................... 9-32 System Versus Exception Interrupts ........9-32 Functional Description ............
Page 27 Contents Effect Latency ................9-42 Write Effect Latency .............. 9-42 Signal Routing Unit Effect Latency ........9-42 Programming Model ..............9-42 DAI Example System ............. 9-43 SERIAL PORTS Features ..................10-2 Pin Descriptions ................. 10-4 SRU Programming ..............10-5 SRU SPORT Receive Master ..........10-6 SRU SPORT Signal Integrity ..........
Page 28 Contents Frame Sync and Data Sampling ........10-16 Serial Word Length ............10-18 Internal Versus External Frame Syncs ......10-18 External Frame Sync Sampling ........10-19 Logic Level Frame Syncs ..........10-20 Data-Independent Frame Sync ........10-20 Operation Modes ..............10-21 Mode Selection ..............
Page 29 Contents Frame Sync Delay (MFD) ..........10-33 Transmit Data Valid Signal ..........10-33 Transmit Data Valid Output ........10-34 Timing Control Bits ............10-35 Number of Channels (NCH) ........... 10-35 Active Channel Selection Registers ........10-36 Companding Selection ............ 10-36 Companding Limitations (ADSP-2146x) ......
Page 30 Contents DMA Chaining ..............10-47 DMA Chain Insertion Mode ..........10-48 Frame Sync Generation ........... 10-48 Interrupts ................. 10-49 Internal Transfer Completion ..........10-50 Shared Channels ..............10-50 Error Detection ..............10-51 Error Status ................ 10-53 Debug Features ................. 10-53 SPORT Loopback ...............
Page 31 Contents INPUT DATA PORT Features ..................11-2 Pin Descriptions ................. 11-3 SRU Programming ..............11-5 Register Overview ............... 11-5 Clocking ..................11-6 Functional Description ............... 11-6 Operating Modes ................ 11-8 PDAP Port Selection ............. 11-9 Data Hold ................11-9 PDAP Data Masking ............11-10 PDAP Data Packing ............
Page 32 Contents Standard DMA ............... 11-20 Ping-Pong DMA ............. 11-21 Multichannel DMA Operation ........11-21 Multichannel FIFO Status ..........11-22 Interrupts ................. 11-23 Interrupt Acknowledge ............11-23 Threshold Interrupts ............11-23 DMA Interrupts ..............11-24 FIFO Overflow Interrupts ........... 11-24 Debug Features ................. 11-25 Status register Debug ............
Page 33 Contents ASYNCHRONOUS SAMPLE RATE CONVERTER Features ..................12-2 Pin Descriptions ................. 12-3 SRU Programming ..............12-3 Register Overview ............... 12-4 Clocking ..................12-5 Functional Description ............... 12-5 Serial Data Ports ..............12-9 Operating Modes ................ 12-9 TDM Daisy Chain Mode ............ 12-10 TDM Input Daisy Chain ..........
Page 34 Contents Write Effect Latency ............12-17 SRC Effect Latency ............. 12-18 SONY/PHILIPS DIGITAL INTERFACE Features ..................13-2 Pin Descriptions ................. 13-3 SRU Programming ..............13-4 Register Overview ............... 13-6 Clocking ..................13-7 S/PDIF Transmitter ..............13-7 Functional Description ............13-7 Input Data Format ............
Page 35 Contents Clock Recovery Modes ............ 13-18 Digital On-Chip PLL ..........13-18 External Analog PLL ........... 13-19 Interrupts ................. 13-19 Transmitter Interrupt ............13-19 Receiver Interrupts .............. 13-20 Receiver Error Interrupts ............. 13-20 Debug Features ................. 13-21 Loop Back Routing .............. 13-21 Effect Latency ................
Page 36 Contents Frame Sync Output ............14-7 Divider Mode Selection ............ 14-8 Phase Shift ............... 14-8 Pulse Width ..............14-9 Default Pulse Width ............14-10 Timing Example for I2S Mode ........14-11 Operating Modes ..............14-11 Normal Mode ..............14-12 Bypass Mode ............... 14-13 One-Shot Mode ..............
Page 37 Contents SRU Programming ..............15-4 Register Overview ............... 15-5 Clocking ..................15-6 Choosing the Pin Enable for the SPI Clock ......15-7 Functional Description ............... 15-8 SPI Transaction ..............15-9 Single Master Systems ............15-10 Multi Master Systems ............15-11 Operating Modes ..............
Page 38 Contents Interrupt Sources ..............15-24 Multi Master Error .............. 15-26 Debug Features ................. 15-27 Shadow Receive Buffers ............15-27 Internal Loopback Mode ............. 15-28 Loop Back Routing ............15-28 Effect Latency ................15-28 Write Effect Latency ............15-29 SPI Effect Latency ............... 15-29 Programming Model ..............
Page 39 Contents PERIPHERAL TIMERS Features ..................16-2 Pin Descriptions ................. 16-3 SRU Programming ..............16-3 Register Overview ............... 16-4 Read-Modify-Write ............... 16-5 Clocking ..................16-5 Functional Description ............... 16-5 Operating Modes ................ 16-7 Pulse Width Modulation Mode (PWM_OUT) ....... 16-8 PWM Waveform Generation ........... 16-10 Single-Pulse Generation ..........
Page 40 Contents Programming Model ..............16-21 PWM Out Mode ..............16-21 WDTH_CAP Mode ............16-22 EXT_CLK Mode ..............16-23 SHIFT REGISTER – ADSP-2147X Features ..................17-2 Pin Descriptions ................. 17-3 SRU Programming ..............17-3 Register Overview ............... 17-4 Clocking ..................17-4 Functional Description ...............
Page 41 Contents Functional Description ............... 18-4 Interrupts ................. 18-10 WATCHDOG TIMER – ADSP-2147X Features ..................19-2 Pin Descriptions ................. 19-3 Register Overview ............... 19-3 Clocking ..................19-4 Functional Description ............... 19-4 Operating Mode ................. 19-6 Trip Count ................19-6 Debug Features ................19-7 Emulation Considerations .............
Page 42 Contents Operating Modes ................ 20-8 Data Packing ................ 20-8 9-Bit Transmission Mode ............20-8 Packed Mode ..............20-9 Data Transfer Types ..............20-10 Data Buffers ............... 20-10 Transmit Holding Registers (UARTTHR) ....... 20-10 Receive Buffer Registers (UARTRBR) ......20-11 Core Transfers ..............20-12 DMA Transfers ..............
Page 43 Contents UART Effect Latency ............20-21 Programming Model ..............20-21 Autobaud Detection ............20-21 Programming Model for DMA Transfers ......20-22 Setting Up and Starting Chained DMA ......20-22 Notes on Using UART DMA .......... 20-23 Programming Model for Core Transfers ........ 20-24 TWO WIRE INTERFACE CONTROLLER Features ..................
Page 44 Contents Operating Modes ..............21-14 General Call Addressing ............21-14 Fast Mode ................21-15 Interrupts ................. 21-15 Interrupt Routing ............... 21-16 DPI ................21-16 TWI ................21-16 Interrupt Sources ..............21-17 Debug Features ................. 21-18 Buffer Hang Disable ............21-18 Loop Back Routing .............
Page 45 Contents POWER MANAGEMENT Features ..................22-1 Register Overview ............... 22-1 Phase-Locked Loop (PLL) ............22-2 Functional Description ............22-2 PLL Input Clock ..............22-3 Pre-Divider Input ..............22-3 PLL Multiplier ..............22-4 PLLM Hardware Control ..........22-4 PLLM Software Control ............ 22-4 PLL VCO ................
Page 46 Contents DAI Routing Unit ............... 22-10 External Port Control ............22-11 Disabling the SDRAM Controller ........22-11 Disabling the DDR2 Controller .......... 22-11 Disconnect DAI/DPI Pin Buffers ........22-12 Disable the S/PDIF Reciever ..........22-12 Example for Clock Management .......... 22-12 General Notes on Power Savings ..........
Page 47 Contents External Port Booting ............23-8 SPI Port Booting ..............23-12 Master Boot Mode ............23-12 Master Header Information ..........23-14 Slave Boot Mode ............. 23-15 SPI Boot Packing ............23-17 32-Bit SPI Packing ............23-18 16-Bit SPI Packing ............23-19 8-Bit SPI Packing ............
Page 48 Contents External Port Pin Multiplexing ..........23-29 Multiplexed External Port Pins ........23-30 Backward Compatibility ..........23-31 Parallel Connection of Flag Pins via External Port and DPI Pins 23-31 High Frequency Design ............23-33 Circuit Board Design ............23-33 Clock Input Specifications and Jitter ....... 23-33 RESETOUT ..............
Page 49 Contents REGISTERS REFERENCE Overview ..................A-2 Register Diagram Conventions ..........A-2 Bit Types and Settings ............A-3 System and Power Management Registers ........A-4 System Control Register (SYSCTL) ......... A-4 ADSP-2146x Power Management Registers ......A-6 Power Management Control Registers (PMCTL) ....A-7 Power Management Control Register 1 (PMCTL1) ..............
Page 50 Contents DDR2 Control Register 5 (DDR2CTL5) ......A-35 Refresh Rate Control Register (DDR2RRC) ...... A-36 Controller Status Register 0 (DDR2STAT0) ...... A-37 Controller Status Register 1 (DDR2STAT1) ..... A-39 DLL0 Control Register 1 (DLL0CTL1) ......A-40 DLL1 Control Register 1 (DLL1CTL1) ......A-41 DLL Status Registers (DLL0STAT0, DLL1STAT0) ...
Page 51 Contents DMA Control (MTMCTL Register) ........ A-66 Pulse Width Modulation Registers ........A-67 Global Control Register (PWMGCTL) ......A-67 Global Status Register (PWMGSTAT) ......A-69 Control Register (PWMCTLx) ......... A-69 Status Registers (PWMSTATx) ......... A-71 Output Disable Registers (PWMSEGx) ......A-71 Polarity Select Registers (PWMPOLx) ......
Page 52 Contents FIR Debug Registers (FIRDEBUGCTL, FIRDBGADDR) ............A-86 IIR Accelerator Registers ............A-87 IIR Global Control Register (IIRCTL1) ......A-87 IIR Channel Control Register (IIRCTL2) ......A-90 IIR MAC Status Register (IIRMACSTAT) ......A-91 IIR DMA Status Register (IIRDMASTAT) ......A-91 IIR Debug Registers (IIRDEBUGCTL, IIRDEBUGADDR) ............
Page 53 Contents Local Buffer Configuration Registers (MLB_LCBCRx) ............. A-112 Watchdog Timer Registers ..........A-114 Control (WDTCTL) ............A-114 Status (WDTSTATUS) ..........A-114 Current Count (WDTCURCNT) ........A-115 Trip Counter (WDTTRIP) ..........A-115 Clock Select (WDTCLKSEL) ......... A-116 Period (WDTCNT) ............A-117 Unlock (WDTUNLOCK) ..........
Page 54 Contents DAI Pin Buffer Registers ............. A-148 Pin Buffer Registers (DAI_PIN_STAT) ......A-148 Interrupt Controller Registers ..........A-149 Peripherals Routed Through the DAI ........A-150 Serial Port Registers ............. A-150 SPORT Divisor Registers (DIVx) ........A-151 Serial Control Registers (SPCTLx) ........A-151 SPORT Control 2 Registers (SPCTLNx) ......
Page 55 Contents Mute Register (SRCMUTE) ........... A-189 Ratio Registers (SRCRATx) ..........A-189 Precision Clock Generator Registers ........A-191 Control Registers (PCG_CTLxy) ........A-191 Clock Inputs ..............A-193 Pulse Width Registers (PCG_PWx) ........ A-194 PCG Frame Synchronization Registers (PCG_SYNCx) ... A-196 Sony/Philips Digital Interface Registers ....... A-199 Transmitter Registers ............
Page 56 Contents Stopwatch Count Register (RTC_SWTCH) ....A-213 Clock Register (RTC_CLOCK) ........A-214 Alarm Register (RTC_ALARM) ........A-214 Initialization Register (RTC_INIT) ......... A-215 Initialization Status Register (RTC_INITSTAT) ....A-216 Shift Register Register ............A-217 Control Register (SR_CTL) ..........A-217 DPI Signal Routing Unit Registers ..........A-218 Miscellaneous Signal Routing Registers (SRU2_INPUTx, Group A) ..........
Page 57 Contents UART Control and Status Registers ........A-243 Line Control Register (UART0LCR) ......A-243 Line Status Register (UART0LSR) ........A-245 Interrupt Enable Register (UART0IER) ......A-246 Interrupt Identification Registers (UART0IIR, UART0IIRSH) ............A-247 Divisor Latch Registers (UART0DLL, UART0DLH) ..A-249 Scratch Register (UART0SCR) ........
Page 58 Contents Interrupt Enable Register (TWIIMASK) ......A-267 Peripheral Timer Registers ........... A-269 Read-Modify-Write Timer Control Register ....A-269 Timer Configuration Registers (TMxCTL) ...... A-270 Timer Status Registers (TMxSTAT) ........ A-271 Register Listing ................. A-273 PERIPHERAL INTERRUPT CONTROL Interrupt Latency ................. B-1 Interrupt Acknowledge ..............
Page 59 Contents Subframe Format ..............C-12 Channel Coding ..............C-14 Preambles ................C-15 INDEX ADSP-214xx SHARC Processor Hardware Reference -lix www.BDTIC.com/ADI...
Page 60 Contents ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 61: Preface
The ADSP-214xx SHARC Processor Hardware Reference contains informa- tion about the DSP architecture and DSP assembly language for these processors. These are 32-bit, fixed- and floating-point digital signal pro- cessors from Analog Devices for use in computing, communications, and consumer applications. Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors.
Page 62: Manual Contents
Manual Contents Manual Contents This manual provides detailed information about the ADSP-214xx pro- cessors in the following chapters: • Chapter 1, “Introduction” Provides an architectural overview of the SHARC processors. • Chapter 2, “I/O Processor” Describes input/output processor architecture, and provides direct memory access (DMA) procedures for the processor peripherals.
Page 63 Preface • Chapter 8, “Media Local Bus” Details the Media Local Bus port (MLB), an on-PCB or inter-chip communication bus, which allows an application to access MOST network data. • Chapter 9, “Digital Application/Digital Peripheral Interfaces” Provides information about the digital audio/digital peripheral interface (DAI/DPI) which allows you to attach an arbitrary num- ber and variety of peripherals to the SHARC processor while retaining high levels of compatibility.
Page 64 Manual Contents • Chapter 15, “Serial Peripheral Interface Ports” Describes the operation of the serial peripheral interface (SPI) port. SPI devices communicate using a master-slave relationship and can achieve high data transfer rate because they can operate in full-duplex mode. •...
Page 65: What's New In This Manual
Preface • Chapter 23, “Power Management” Describes system design features as they relate to power management. • Appendix A, “Registers Reference” Provides a graphical presentation of all registers and describes the bit usage in each register. • Appendix B “Peripheral Interrupt Control” Provides a complete listing of the registers that are used to config- ure and control interrupts.
Page 66: Technical Or Customer Support
P.O. Box 9106 Norwood, MA 02062-9106 Registration for MyAnalog.com is a free feature of the Analog Devices Web site that allows MyAnalog.com customization of a Web page to display only the latest information about products you are interested in. Click Register to use this site...
Page 67: Engineerzone
If you are already a registered user, just log on. Your user name is your e-mail address. EngineerZone EngineerZone is a technical support forum from Analog Devices. It allows you direct access to ADI technical support engineers. You can search FAQs and technical information to get quick answers to your embedded processing and DSP design questions.
Page 68: Product Information
Product Information Product Information Product information can be obtained from the Analog Devices Web site, VisualDSP++ online Help system, and a technical library CD. Analog Devices Web Site The Analog Devices Web site, , provides information www.analog.com about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.
Page 69: Technical Library Cd
CD check mark, and fill out the order form. Data sheets, which can be downloaded from the Analog Devices Web site, change rapidly, and therefore are not included on the technical library CD. Technical manuals change periodically. Check the Web site for the latest manual revisions and associated documentation errata.
Page 70: Notation Conventions
Notation Conventions Notation Conventions Text conventions used in this manual are identified and described as fol- lows. Note that additional conventions, which apply only to specific chapters, may appear throughout this document. Example Description Close command Titles in reference sections indicate the location of an item within the (File menu) VisualDSP++ environment’s menu system (for example, the Close com- mand appears on the File menu).
Page 71 Preface Example Description Note: For correct operation, ...  A Note: provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this symbol. Caution: Incorrect device operation may result if ... ...
Page 72 Notation Conventions lxxii ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 73: Introduction
1 INTRODUCTION The ADSP-214xx SHARC processors are high performance 32-bit proces- sors used for high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications. By adding on-chip SRAM, integrated I/O peripherals, and an additional processing element for single-instruc- tion multiple-data (SIMD) support, this processor builds on the ADSP-21xxx family DSP core to form a complete system-on-a-chip.
Page 74: Sharc Family Product Offerings
Processor Architectural Overview SHARC Family Product Offerings The products described in this manual offer a variety of features and per- formance. A complete list of features and specifications can be found in the product specific data sheet. Some models of these products are available with controlled manufactur- ing to support the quality and reliability requirements of automotive applications.
Page 75: I/O Peripherals
Introduction I/O Peripherals These peripherals are coupled with the external port and therefore inde- pendent from the routing units. • Asynchronous Memory Interface (AMI) • SDRAM controller (ADSP-2147x, ADSP-2148x) • DDR2 controller (ADSP-2146x) • 4 PWM modules I/O Processor The input/output processor (IOP) manages the off-chip data I/O to free the core from this burden.
Page 76: Interrupt Controller
Processor Architectural Overview • 4 asynchronous sample rate converters (ASRC) • DTCP encryption Interrupt Controller The DAI contains its own interrupt controller that indicates to the core when DAI audio events have occurred. This interrupt controller offers 32 independently configurable channels. Signal Routing Unit Conceptually similar to a “patch-bay”...
Page 77: Signal Routing Unit 2
Introduction Signal Routing Unit 2 Conceptually similar to a “patch-bay” or multiplexer, the SRU2 provides a group of registers that define the interconnection of the DPI peripherals to the DPI pins or to other DPI peripherals. Development Tools The processors are supported by VisualDSP++, an easy to use Integrated Development and Debugging Environment (IDDE).
Page 78: I/O Architecture Enhancements
Differences from Previous Processors I/O Architecture Enhancements The I/O processor provides much greater throughput than the ADSP-2116x processors. This architecture incorporates two independent DMA buses versus the previous SHARC DMA controllers: • one peripheral DMA bus (IOD0) • one external port DMA bus (IOD1) This allows to operate all external port DMA accesses independently from the peripheral buses since up to four internal memory blocks are address- able without any bus conflicts.
Page 79 2 I/O PROCESSOR In applications that use extensive off-chip data I/O, programs may find it beneficial to use a processor resource other than the processor core to per- form data transfers. The ADSP-214xx processors contain an I/O processor (IOP) that supports a variety of DMA (direct memory access) operations. Each DMA operation transfers an entire block of data.
Page 80: Features
Features Features I/O processor features are briefly described in the following list. • Internal memory ↔ SPORT (DAI) • SPORT (DAI) ↔ External Memory • Internal memory ← IDP (DAI) unidirectional • Internal memory ↔ SPI • Internal memory ↔ Link port •...
Page 81: Register Overview
I/O Processor Register Overview Two global IOP registers control the DMA arbitration over the I/O buses—the first for the peripheral bus and the second for the external port bus. This section provides brief descriptions of the major IOP registers. For complete information, see “Register Listing”...
Page 82: Standard Dma Parameter Registers
DMA Channel Registers Standard DMA Parameter Registers The parameter registers described below control the source and destina- tion of the data, the size of the data buffer, and the step size used.  The length of DMA registers for the serial ports have changed from earlier SHARC processors in order to accommodate data transfers to/from external memory.
Page 83 I/O Processor Table 2-2. Index Registers (Cont’d) Register Name Width (Bits) Description OIIIR Accelerator IIR output IIFFT Accelerator FFT input OIFFT Accelerator FFT output IIMTMW MTM Write IIMTMR MTM Read IIEP0–1 External Port0–1 EIEP0–1 External Port (external) Modify registers. These registers, shown in Table 2-3, provide the signed increment by which the DMA controller post-modifies the corresponding...
Page 84 DMA Channel Registers Table 2-3. Modify Registers (Cont’d) Register Name Width (Bits) Description IMIIR Accelerator IIR data input CMIIR Accelerator IIR coeff input OMIIR Accelerator IIR output IMFFT Accelerator FFT input OMFFT Accelerator FFT output IMMTMW MTM Write IMMTMR MTM Read IMEP0–1 External Port EMEP0–1...
Page 85 I/O Processor Table 2-4. Count Registers (Cont’d) Register Name Width (Bits) Description ICIIR Accelerator IIR data input CCIIR Accelerator IIR coeff input OCIIR Accelerator IIR output ICFFT Accelerator FFT input OCFFT Accelerator FFT output ICMTMW MTM Write ICMTMR MTM Read ICEP0–1 External Port ECEP0–1...
Page 86: Extended Dma Parameter Registers
DMA Channel Registers Table 2-5. Chain Pointer Registers (Cont’d) Register Name Width (Bits) Description CPFIR Accelerator FIR CPIIR Accelerator IIR CPIFFT Accelerator FFT input CPOFFT Accelerator FFT output CPEP0–1 External Port Extended DMA Parameter Registers This section describes the enhanced parameter registers used for Accelera- tor and External Port.
Page 87 I/O Processor Table 2-7. Length Registers Register Name Width (Bits) Description ILFIR Accelerator FIR input OLFIR Accelerator FIR output ILIIR Accelerator IIR input OLIIR Accelerator IIR output ILFFT Accelerator FFT input OLFFT Accelerator FFT output ELEP0–1 External Port (external base) Miscellaneous External Port Parameter registers.
Page 88: Data Buffers
DMA Channel Registers Data Buffers The data buffers or FIFOs (shown in Table 2-9) are used by each DMA channel to store data during the priority arbitration time period. The buf- fers (depending on the peripheral) are accessed by both DMA and the core.
Page 89: Chain Pointer Registers
I/O Processor Table 2-9. Data Buffers (Cont’d) Buffer Name FIFO Depth Description UARTRBR0 UART0 Receiver UARTTHR0 UART0 Transmitter Accelerator input FFT DMA only Accelerator output FFT DMA only MTM read/write DMA only DFEP0–1 DMA only AMIRX AMI Receive Packer AMITX AMI Transmit Packer TXTWI8 1 (1 byte)
Page 90 DMA Channel Registers Table 2-10. Chain Pointer Register (CPx) Name Description 18–0 IIx address Next chain pointer address Program controlled interrupt 0 = no interrupt after current TCB 1 = interrupt after current TCB  For the new SPORT external memory functionality, when writing tests which involve the bit, the external memory address should be split before writing to the chain pointer register.
Page 91: Tcb Storage
I/O Processor Table 2-13. FFT Input Chain Pointer Register (CPIFFT) Name Description 18–0 IIx address Next chain pointer address Program controlled interrupt 0 = no interrupt after current TCB 1 = interrupt after current TCB COEFFSEL Coefficient select for next TCB 0 = next TCB is data TCB 1 = next TCB is coeff TCB Bit 19 of the chain pointer register is the program controlled interrupt...
Page 92: Serial Port Tcb
TCB Storage Serial Port TCB The serial ports support single and chained DMA. Table 2-14 shows the required TCBs for chained DMA Table 2-14. SPORT TCBs Address Register CP[27:0] CPSPx Chain Pointer CP[27:0] + 0x1 ICSPx Internal Count CP[27:0] + 0x2 IMSPx Internal Modifier CP[27:0] + 0x3 IISPx Internal/External Index...
Page 93: Uart Tcb
I/O Processor UART TCB The UART interface supports both single and chained DMA. However, unlike the serial ports, programs cannot insert a TCB in an active chain. Table 2-16 shows the required TCBs for chained DMA. Table 2-16. UART0 TCBs Address Register CP[18:0]...
Page 94: Fir Accelerator Tcb
TCB Storage FIR Accelerator TCB The FIR accelerator DMA supports circular buffer chained DMA. Table 2-18 shows the required TCBs for chained DMA. The FIR acceler- ator does not support circular buffering for the coefficient buffer. Table 2-18. FIR TCBs Address Register CP[18:0]...
Page 95: Iir Accelerator Tcb
I/O Processor IIR Accelerator TCB The IIR accelerator supports circular buffer chained DMA. Table 2-19 shows the required TCBs for chained DMA.  In the IIR accelerator DMA, two different TCB loading sequences are available: one TCB loads five parameters for the coefficients ).
Page 96: Fft Accelerator Tcb
TCB Storage FFT Accelerator TCB The FFT accelerator supports circular buffer chained DMA. Table 2-20 Table 2-21 shows the required TCBs for chained DMA. Table 2-20. FFT Input TCBs Address Register CP[18:0] CPIFFT CP[18:0] + 0x1 IBFFT CP[18:0] + 0x2 ILFFT CP[18:0] + 0x3 ICFFT...
Page 97: External Port Tcb
I/O Processor External Port TCB The external port interface supports many different types of DMA, result- ing in different lengths of TCBs. The TCB size varies from six locations (chained DMA) to 13 locations (delay line DMA). Table 2-22 shows the required TCBs for chained DMA.
Page 98 TCB Storage For delay line DMA, TCB loading is split into two sequences to improve overall priority. The first TCB loads the write parameters ( – ) and IIEP ELEP the second loads the read parameters ( – ). This two stage loading RIEP CPEP is transparent to the application.
Page 99 I/O Processor The order the descriptors are fetched for scatter/gather DMA with circular buffering enabled is shown in Table 2-25 Table 2-26. Table 2-25. External Port TCBs for Scatter/Gather DMA Address Register CP[18:0] CPEP CP[18:0] + 0x1 TPEP CP[18:0] + 0x2 TCEP CP[18:0] + 0x3 EMEP...
Page 100: Clocking
Clocking Clocking The fundamental timing clock of the IOP is peripheral clock ( ). All PCLK DMA data transfers over the IO0 or IO1 buses are clocked at speed. PCLK Functional Description The following several sections provide detail on the function of the I/O processor.
Page 101: Dma Transfer Types
I/O Processor DMA Transfer Types Standard DMA. A standard DMA (once it is configured) transfers data from location A to location B. An interrupt can be used to indicate the end of the transfer. To start a new DMA sequence after the current one is finished, a program must first clear the DMA enable bit (control register), write new parameters to the index, modify, and count registers (parameter registers), then set the DMA enable bit to re-enable DMA (control...
Page 102: Dma Direction
Functional Description A. When the transfer is completed as per the value in the count register, the DMA restarts with the memory location indexed by B. The DMA restarts with index A after the transfer to memory with index B is com- pleted as per the count value.
Page 103: Peripheral To External Memory (Sports)
I/O Processor The direction (receive or transmit) of the peripheral determines the direc- tion of data transfer. When the port receives data, the I/O processor automatically transfers the data to internal memory. When the port needs to transmit a word, the I/O processor automatically fetches the data from internal memory.
Page 104 Functional Description DMA ADDRESS GENERATOR (INTERNAL ADDRESSES) LOCAL BUS INTERNAL MODIFIER INDEX (ADDRESS) MEMORY ADDRESS POST-MODIFY DMA WORD COUNTER LOCAL BUS COUNT CHAIN POINTER – 1 WORKING REGISTER DMA ADDRESS GENERATOR (EXTERNAL ADDRESSES) LOCAL BUS EXTERNAL EXTERNAL EXTERNAL EXTERNAL MEMORY INDEX (ADDRESS) MODIFIER COUNT...
Page 105: Internal Index Register Addressing
I/O Processor Internal Index Register Addressing All addresses in the index registers are offset by a value matching the pro- cessor’s first internal normal word addressed RAM location, before the I/O processor uses the addresses. For the ADSP-214xx processors, this off- set value is 0x0008 0000.
Page 106: External Index Register Addressing
Functional Description occurs because the I/O processor starts the first transfer before test- ing the count value. The only way to disable a DMA channel is to clear its DMA enable bit. External Index Register Addressing The external port DMA channels each contain additional parameter regis- ters: the external index registers ( ), external modify registers ( EIEPx...
Page 107: Dma Start And Stop Conditions
I/O Processor The peripheral’s DMA controller tracks status information of the channels in each of the peripheral registers (for example SPMCTLx SPIDMACx , and DAI_STAT DMACx MTMCTL • DMA channel status (status bit is set until the DMA terminates) • TCB chain loading status (status bit is set until TCB loading completes) If polling the status of a chained DMA, the DMA status bit is first set when the TCB has terminated, then it is cleared.
Page 108: Operating Modes
Operating Modes A DMA sequence ends when one of the following occurs. • The count register decrements to zero, and the chain pointer regis- ter is zero. • Chaining is disabled and the channel’s DMA enable bit transitions from high to low. If the DMA enable bit goes low (=0) and chain- ing is enabled, the channel enters chain insertion mode (SPORT only) and the DMA sequence continues.
Page 109 I/O Processor INTERNAL MEMORY I/F ARBITER IOD1 BUS IOD0 BUS I/O SPEP EXTERNAL PERIPHERAL PORT ARBITER ARBITER SPORT EP (SPEP) ARBITER IOD1 IOD0 EXTERNAL PORT DMA BUS PERIPHERAL DMA BUS CORE BUS DDR2 LINK SPORTx UART PORT SDRAM Figure 2-2. I/O Processor Bus Structure ...
Page 110: Dma Chaining
Operating Modes DMA Chaining DMA data transfers can be set up as continuous or periodic. Furthermore, these DMA transfers can be configured to run automatically using chained DMA. With chained DMA, the attributes of a specific DMA are stored in internal memory and are referred to as a Transfer Control Block or TCB.
Page 111: Chain Assignment
I/O Processor Table 2-27. Principal TCB Allocation for a Serial Peripheral (Cont’d) Address Register Description CPx + 0x2 (IMx) Internal modify register Stride for internal buffer CPx + 0x3 (IIx) Internal index register Internal memory buffer Chain Assignment The structure of a TCB is conceptually the same as that of a traditional linked-list.
Page 112: Starting Chain Loading
Operating Modes Listing 2-1. Chain Assignment R0=0; dm(CPx)=R0; /* clear CPx register */ /* init DMA control registers */ R2=(TCB1+3) & 0x7FFFF; /* load IIx address of next TCB and mask address */ R2=bset R2 by 19; /* set PCI bit */ dm(TCB2)=R2;...
Page 113: Tcb Chain Loading Priority
I/O Processor During TCB chain loading, the I/O processor loads the DMA channel parameter registers with values retrieved from internal memory.  When starting chain loading, note that the SPI port is an exception to the above. To execute the first DMA in a chain for this periph- eral, the DMA parameter registers also need to be explicitly programmed.
Page 114: Chain Insert Mode (Sports Only)
Operating Modes Chain Insert Mode (SPORTs Only) It is possible to insert a single SPORT DMA operation or another DMA chain within an active SPORT DMA chain. Programs may need to per- form insertion when a high priority DMA requires service and cannot wait for the current chain to finish.
Page 115 I/O Processor Table 2-28. DMA Channel 0–66 Priorities (Cont’d) Peripheral Control/Status Parameter Data Buffer Description Channel Group Registers Registers Number SPCTL3, IISP3A, IMSP3A, RXSP3A or Serial Port 3A Data SPMCTL3 CSP3A, CPSP3A TXSP3A IISP3B, IMSP3B, RXSP3B or Serial Port 3B Data CSP3B, CPSP3B TXSP3B SPCTL2,...
Page 116 Operating Modes Table 2-28. DMA Channel 0–66 Priorities (Cont’d) Peripheral Control/Status Parameter Data Buffer Description Channel Group Registers Registers Number IDP_CTL, IDP_DMA_I0, IDP_FIFO DAI IDP or IDP_CTL1, IDP_DMA_M0, PDAP IDP_CTL2, IDP_DMA_C0, (only channel 0 IDP_PP_CTL, IDP_DMA_I0A, supports both DAI_STAT IDP_DMA_I0B, IDP_DMA_PC0 IDP_DMA_I1, Serial Input DAI...
Page 117 I/O Processor Table 2-28. DMA Channel 0–66 Priorities (Cont’d) Peripheral Control/Status Parameter Data Buffer Description Channel Group Registers Registers Number IDP_CTL, IDP_DMA_I5, IDP_FIFO Serial Input DAI IDP_CTL1, IDP_DMA_M5, IDP Channel 5 IDP_CTL2, IDP_DMA_C5, IDP_PP_CTL, IDP_DMA_I5A, DAI_STAT IDP_DMA_I5B, IDP_DMA_PC5 IDP_DMA_I6, Serial Input DAI IDP_DMA_M6, IDP Channel 6 IDP_DMA_C6,...
Page 118 Operating Modes Table 2-28. DMA Channel 0–66 Priorities (Cont’d) Peripheral Control/Status Parameter Data Buffer Description Channel Group Registers Registers Number UART0RXCTL, IIUART0RX, UARTRBR0 Buf- UART0 Receive UART0RXSTAT IMUART0RX, Buffer Register CUART0RX, CPUART0RX, UART0TXCTL, IIUART0TX, UARTTHR0 UART0 Transmit UART0TXSTAT IMUART0TX, Buffer Holding Register CUART0TX, CPUART0TX,...
Page 119 I/O Processor Table 2-28. DMA Channel 0–66 Priorities (Cont’d) Peripheral Control/Status Parameter Data Buffer Description Channel Group Registers Registers Number PMCTL1, IIFIR, IMFIR, Accelerator Input FIR, IIR, FFT FIRCTL1, ICFIR, IBFIR, Buffers and FIFO Accelerator Input FIRCTL2, CIFIR, CMFIR, Data FIRMACSTAT, CLFIR, CPFIR FIRDMASTAT...
Page 120: Peripheral Dma Bus
Operating Modes Table 2-28. DMA Channel 0–66 Priorities (Cont’d) Peripheral Control/Status Parameter Data Buffer Description Channel Group Registers Registers Number IOD1 External Port Bus DMAC0 IIEP0, IMEP0, DFEP0 External Port ICEP0, EIEP0, Memory DMA 0 EMEP0 ELEP0, AMIRX EBEP0 RIEP0, AMITX RCEP0 RMEP0, (AMI only)
Page 121: External Port Dma Bus
I/O Processor In the fixed priority scheme, the lower indexed peripheral has the highest priority. External Port DMA Bus External port DMA channels transfer data between internal memories or between internal and external memory over the IOD1 bus. When both external port channels request access to the IOD1 bus in a clock cycle, the external port bus arbiter, which is attached to the IOD1 bus, determines which master should have access to the bus and grants the bus to that...
Page 122: Rotating Dma Channel Arbitration
Operating Modes External port/SPORT channel arbitration can be set to use either a fixed or rotating algorithm by setting the bits in the register as EPBR EPCTL follows. • (00) = Priority order from highest to lowest is SPORT, external port DMA, core.
Page 123: Interrupts
I/O Processor is in group A), SP1 has the highest priority. Programs can change DMA arbitration modes between fixed and rotate on the fly which incurs an effect latency of 2 cycles. PCLK Interrupts The primary type of DMA communication is interrupt driven I/O where the core continues to execute instructions while DMA executes in the background.
Page 124: Chained Dma Interrupts
Interrupts Chained DMA Interrupts For chained DMA, the channel generates interrupts in one of two ways: 1. If = 1, (bit 19 of the chain pointer register is the program con- trolled interrupts, or bit) an interrupt occurs for each DMA in the chain.
Page 125: Internal Transfer Completion
I/O Processor Internal Transfer Completion This mode of interrupt generation resembles the traditional SHARC DMA interrupt generation. The interrupt is generated once the DMA internal transfers are complete, independent of whether the DMA is a transmit or receive. Therefore, for external transmit DMAs, when the completion interrupt is generated there may still be an external access pending at the external DMA interface.
Page 126: Interrupt Versus Channel Priorities
Interrupts interrupt-driven I/O under control of the processor core. Refer to the spe- cific peripheral chapter for more information. Interrupt Versus Channel Priorities At their default setting shown in Table 2-29, the DMA interrupt priorities do not match the DMA channel priorities. However, if both priorities schemes should match, the DMA interrupt priorities can be re-assigned by dedicated settings of the registers.
Page 127: Debug Features
I/O Processor Debug Features The JTAG interface provides some user debug features for DMA in that it allows programs to place breakpoints on the IOD buses. Programmers can then insert DMA related breakpoints. For more information, see the Visu- alDSP tools documentation and the SHARC Processor Programming Reference.
Page 128: Iop Throughput
Programming Model IOP Throughput Since the I/O processor controls two I/O buses (peripheral and external port) the maximum bandwidth per IOD bus is gained for: • Internal memory writes with f × 32-bit PCLK • Internal memory reads with f /2 ×...
Page 129: General Procedure For Configuring Dma
I/O Processor General Procedure for Configuring DMA To configure the processors to use DMA, use the following general proce- dure. Note this is a generic model. For specific information refer to the individual programming model section in the peripheral specific chapter. 1.
Page 130 Programming Model 2-52 ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 131: External Port
3 EXTERNAL PORT The external memory interface provides a glueless interface to external memories. The asynchronous memory interface and the SDRAM/DDR2 memory that interfaces to the external port is clocked by the SDRAM or DDR2 clock. The interface specifications are shown in Table 3-1.
Page 132: Features
Features Table 3-1. External Port Specifications (Cont’d) Feature SDRAM Interface DDR2 Interface DMA Data Access DMA Channels DMA Chaining Boot Capable Clock Operation SDCLK or SDCLK DDR2CLK DDR2CLK Features The external port has the following features. • Supports access to the external memory by core and DMA accesses. The external memory address space is divided in to four banks.
Page 133: Pin Descriptions
External Port • Arbitration Logic to coordinate core, SPORT DMA, external port DMA, transfers between internal and external memory over the external port. • External port supports various ratios of core to external port clock determined by programming bits in the power management con- trol registers ( For more information, see PMCTL...
Page 134 Register Overview External Port Control Register (EPCTL). This register enables the exter- nal banks for the SDRAM or the AMI. Moreover controls accesses between the processor core and DMA, and between different DMA channels. Power Management Control Register (PMCTL). Controls the SDCLK to core clock ratio related to the AMI or SDRAM timing.
Page 135: Clocking Ami/Sdram
External Port DDR2 Refresh Control Register (DDR2RRC). The DDR2 refresh rate control register provides a programmable refresh counter which has a period based value which coordinates the supplied clock rate with the DDR2 device's required refresh rate. DDR2 DLL Control Registers (DLL1-0CTL1). A built-in DLL in the DDR2 controller provides a 90º...
Page 136: Clocking Ami/Ddr2
Clocking AMI/DDR2  The SDRAM clock ratio settings are independent from the periph- eral clock ( PCLK Table 3-2. External Port Clock Frequencies CCLK:SDCLK CCLK = 400 CCLK = 333 CCLK = 266 CCLK = 200 Clock Ratio 1:2.0 1:2.5 1:3.0 1:3.5 1:4.0...
Page 137: External Port Arbitration
External Port External Port Arbitration The external port arbiter is a key componant of the module. The arbiter performs the following functions. • Controls the speed for the AMI SDRAM/DDR2 • Controls the external banks individually • Performs access arbitration for AMI, SDRAM/DDR2 and SPORT access •...
Page 138 Functional Description EP CORE BUS SPEP (SPORT) BUS ARBITER PERIPHERAL CONTROLLER CORE BUS EP IOP REGISTER ADDR DATA/MSx IOD1 (EP) SDRAM DMA BUS SDRAM CONTROLLER ARBITER ARBITER SDA10, DQM Figure 3-1. External Port Functional Block Diagram (SDRAM) Figure 3-2 shows a diagram of the external port for the ADSP-2146x pro- cessor (containing a DDR2 interface).
Page 139 External Port AMI_MS EP CORE BUS AMI_WR SPEP (SPORT) BUS AMI_RD ARBITER AMI_ADDR PERIPHERAL CORE BUS AMI_DATA EP IOP REGISTER DDR2_ DDR2_ DDR2_ DDR2_ DDR2_ IOD1 (EP) DDR2_ DMA BUS DDR2 DDR2_ DDR2 ARBITER CONTROLLER ARBITER DDR2_ DDR2_ DDR2_ DDR2_ DDR2_ DDR2_ DDR2...
Page 140: Operating Mode
Asynchronous Memory Interface (when all DMA engines are idle and no core or SPORT access to external memory are pending). Operating Mode The following operation mode applies to the external port arbiter. Arbitration Freezing Arbitration length freezing can be used to improve the throughput of read accesses by programming the various freeze bits of the register.
Page 141: Features
External Port Features The AMI has the following features and capabilities. • User defined combinations of programmable wait states • External hardware acknowledge signals • Data packing support for 8 and 16 bits (ADSP-2147x and ADSP-2148x) • External instruction fetch from 8 and 16 bits •...
Page 142: Asynchronous Reads
Asynchronous Memory Interface The external interface follows standard asynchronous SRAM access proto- col. The programmable wait states, hold cycle and idle cycles are provided to interface memories of different access times. To extend access the signal can be pulled low by the external device as an alternative to using wait states.
Page 143 External Port READ STROBE SETUP READ HOLD 1 CYCLE READ WAIT STATES (WS) WAIT STATES (WHS) AMI_ADDR AMI_MSx AMI_RD AMI_DATA STROBE SETUP FOR ACK ADDRESS SETUP FOR ACK AMI_ACK Figure 3-3. AMI Asynchronous Reads STROBE SETUP WRITE HOLD 1 CYCLE WRITE WAIT STATES (WS) CYCLES (H) AMI_ADDR...
Page 144: Parameter Timing
Asynchronous Memory Interface Parameter Timing This section describes the programmable timing parameter for the AMI. The AMI controller allows to program access timing parameters (wait states for idle or hold cycles) with the effect being flexible and efficient whether initiation is from the core or from DMA, and the sequence of transactions (read followed by read, read followed by write, and so on).
Page 145: Operating Modes
External Port Table 3-3. AMI Address Memory Map Bus Width External Internal Logical Address External Physical Address Memory (supported memory map) (on ADDR23–0) Bank ADSP-2146x/ADSP-2147x/ADSP-2148x 8-bit (and 0x0020_0000 – 0x003F_FFFF 0x80_0000 – 0xFF_FFFF PKDIS = 0) 8-bit (and 1, 2, 3 0x0400_0000 –...
Page 146: Predictive Reads
Asynchronous Memory Interface Table 3-4. Data Packing Bit Settings (PKDIS) Packing PKDIS Bit MSWF Bit Description Mode Setting Setting Enabled 8- or 16-bit received data is packed to 32-bit data and transmitted 32-bit data is unpacked to 2 16-bit data or 4 8-bit data.
Page 147: Sdram Controller (Adsp-2147X/Adsp-2148X)
External Port In contrast, when no predictive read ( bit = 1) is used, the delay PREDIS between two reads increases. Note that both DMA and the processor core have predictive read capability. Further note that the bit should PREDIS not be changed when the AMI is performing an access.
Page 148: Functional Description
SDRAM Controller (ADSP-2147x/ADSP-2148x) • Supports up to 254M words of SDRAM memory • No-burst mode (BL = 1) with sequential burst type • Open page policy—any open page is closed only if a new access in another page of the same bank occurs •...
Page 149 External Port internally connected acknowledge signal, as controlled by refresh, or page miss latency overhead. A programmable refresh counter is provided which generates background auto-refresh cycles at the required refresh rate based on the clock fre- quency used. The refresh counter period is specified with the field in RDIV the SDRAM refresh rate control register...
Page 150: Sdram Commands
SDRAM Controller (ADSP-2147x/ADSP-2148x) SDRAM Commands This section provides a description of each of the commands that the SDC uses to manage the SDRAM interface. These commands are handled auto- matically by the SDC. A summary of the various commands used by the on-chip controller for the SDRAM interface follows and is shown in Table 3-5 on page 3-25.
Page 151: Bank Activation
External Port ing 1 to the bit in the register, subsequent SDRAM accesses SDPSS SDCTL initiate the power-up sequence. The exact order of the power-up sequence is determined by the bit of the register. SDPM SDCTL The load mode register command initializes the following parameters. •...
Page 152: Precharge All
SDRAM Controller (ADSP-2147x/ADSP-2148x) Precharge All The precharge all command is given to precharge all internal banks at the same time before executing an auto-refresh. All open banks are automati- cally closed. This is possible since the SDC uses a separate SDA10 which is asserted high during this command.
Page 153 External Port Figure 3-5 Figure 3-6 show the SDRAM write and read timing of the processors. SDCLK COMMAND ADDR BA[1:0] DATA t RCD t WR t RP t RAS t RC Figure 3-5. Write Timing Diagram SDCLK COMMAND ADDR BA[1:0] DATA t RCD t RP...
Page 154: Auto-Refresh
SDRAM Controller (ADSP-2147x/ADSP-2148x) Auto-Refresh The SDRAM internally increments the refresh address counter and causes a CAS before RAS (CBR) refresh to occur internally for that address when the auto-refresh command is given. The SDC generates an auto-refresh command after the SDC refresh counter times out. The value in the RDIV SDRAM refresh rate control register (...
Page 155: Address Mapping
External Port Table 3-5. SDRAM Pin States During SDC Commands Command SDCKE SDCKE MS3–0 SDRAS SDCAS SDWE SDA10 Addresses (n–1) Mode Opcode Opcode register set Activate Valid Valid Read Valid Single Valid Precharge Precharge all Write Valid Auto-refresh Self-refresh entry Self-refresh Self-refresh exit...
Page 156: Address Translation Options
SDRAM Controller (ADSP-2147x/ADSP-2148x) Address Translation Options To provide flexible addressing, the bit (bit 31) in the SDADDRMODE SDCTL0 register is used to select the address mapping scheme—page interleaving or bank interleaving (default). Page Interleaving Map Programming the bit to 1 selects the page interleaving scheme. SDADDRMODE In this scheme consecutive pages fall in consecutive banks.
Page 157: Address Width Settings
External Port  For two-banked SDRAMs, connect BA with A17. Note that page interleaving is not supported with 2 bank devices. CORE ADDRESS MAPPING, TO ROW, COLUMN ADDRESSES (Page Interleaving, SDADDRMODE=1) Bank Row Address Unused Column Address Address CORE ADDRESS MAPPING, TO ROW, COLUMN ADDRESSES (Bank Interleaving, SDADDRMODE=0) Bank Unused Row Address...
Page 158: 16-Bit Address Mapping
SDRAM Controller (ADSP-2147x/ADSP-2148x) Row Address Width (SDRAW). These bits in the register deter- SDCTL mine the row width of the SDRAM. The bits can be programmed SDRAW for row widths of 8 to 15. Column Address Width (SDCAW). The SDRAM memory control regis- ter also includes external bank specific programmable parameters.
Page 159 External Port Table 3-7. Page Interleaving Map (1K Page Size) Column Address Row Address Bank Address Pins of SDRAM A[18] IA[10] BA[1] A[17] IA[9] BA[0] A[13] A[12] IA[23] A[12] A[11] IA[22] A[11] SDA10 1’b0 IA[21] A[10] A[9] IA[8] IA[20] A[9] A[8] IA[7] IA[19]...
Page 160 SDRAM Controller (ADSP-2147x/ADSP-2148x) Table 3-8 where = 0, = 1, = 100 (12 bits), SDADDRMODE X16DE SDRAW2–0 = 11 (11 bits). SDCAW1–0 Table 3-8. Page Interleaving Map (2K Page Size) Column Address Row Address Bank Address Pins of SDRAM A[18] IA[23] BA[1] A[17]...
Page 161 External Port Table 3-9, = 1, = 1, = 101 (13 bits), and SDADDRMODE X16DE SDRAW2–0 = 10 (10 bits). SDCAW Table 3-9. Bank Interleaving Map (1K Page Size) Column Address Row Address Bank Address Pins of SDRAM A[18] IA[10] BA[1] A[17] IA[9]...
Page 162: Refresh Rate Control
SDRAM Controller (ADSP-2147x/ADSP-2148x) Table 3-10 where = 0, = 1, = 100 (12 bits), SDADDRMODE X16DE SDRAW2–0 = 11 (11 bits). SDCAW1–0 Table 3-10. Page Interleaving Map (2K Page Size) Column Address Row Address Bank Address Pins of SDRAM A[18] IA[22] BA[1] A[17]...
Page 163 External Port The delay (in number of cycles) between consecutive refresh coun- SDCLK ter time-outs must be written to the field. A refresh counter time-out RDIV triggers an auto-refresh command to the external SDRAM bank. Programs should write the value to the register before the SDRAM RDIV SDRRC...
Page 164: Internal Sdram Bank Access
SDRAM Controller (ADSP-2147x/ADSP-2148x) • t = 64 ms • NRA = 8192 row addresses • t • t 3 –   × × ×   ------------------------------------------------------------------- RDIV 1030 –  8192  This means is 0x406 (hex) and the SDRAM refresh rate control reg- RDIV ister is written with 0x406.
Page 165: Multibank Access
External Port Multibank Access The processors are capable of supporting multibank operation, thus taking advantage of the SDRAM architecture.  Operation using single versus multibank accesses depends only on the address to be posted to the device, it is NOT an operation mode.
Page 166: Multi Bank Operation With Data Packing
SDRAM Controller (ADSP-2147x/ADSP-2148x) Access to page x Access to page x Bank A Bank A Access to page y Access to page y Bank B Bank B Access to page x Bank C Bank C Access to page y Bank D Bank D Single bank access Multibank access...
Page 167: Timing Parameters
External Port The same SDRAM with page interleaving ( bit = 1) has the fol- SDADDRMODE lowing address map: 0x200000 logical start address int bankA 0x2000FF logical end address int bankA 0x200100 logical start address int bankB 0x2001FF logical end address int bankB 0x200200 logical start address int bankC 0x2002FF logical end address int bankC 0x200300 logical start address int bankD...
Page 168: Data Mask
SDRAM Controller (ADSP-2147x/ADSP-2148x) Data Mask The SDRAM controller provides one pin ( ), all SDRAM SDDQM pins could be connected to pin . The pin is driven high from SDDQM SDDQM reset deassertion until SDRAM initialization completes, after that it’s driven low irrespective of whether any accesses occur.
Page 169: Buffering Controller For Multiple Sdrams
External Port • 8 x 4-bit/page 2k words The SDRAM’s page size is used to determine the system you select. All four systems have the same external bank size, but different page sizes. Note that larger page sizes, allow higher performance but larger page sizes require more complex hardware layouts.
Page 170: Sdram Read Optimization
SDRAM Controller (ADSP-2147x/ADSP-2148x) ADDR [15] CTRL [6] SDRAM BANK 1 ADDR & CTRL SDRAM BANK 2 ADDR & CTRL REGISTERED SDRAM #1 BUFFERS 32M x 4 x 4 SDWE SDCKE A[12-11] OXA[12-0] A[14-0] A[9-0] IXA[12-0] SDA10 DATA [3-0] DATA [3-0] DATA [7-4] DATA[3:0] SDRAM #2...
Page 171: Core Accesses
External Port (bits 20–17) in the register according to the core’s DAG modifier or SDRRC the DMA’s modify parameter register. The predictive address given to the memory depends on the SDMODIFY values. For example, if the DAG modifier = 2, the value should SDMODIFY also be 2, in which case the address + 2 is the predictive value provided to...
Page 172 SDRAM Controller (ADSP-2147x/ADSP-2148x) Listing 3-1. Maximum Throughput Using Sequential Reads ustat1=dm(SDCTL); bit set ustat1 SDROPT|SDMODIFY1; dm(SDCTL)=ustat1; nop; I0 = sdram_addr; M0 = 1; Lcntr = 512, do(PC,1) until lce; R0 = R0 + R1, R0 = dm (I0, M0); The example shows read optimization can be used efficiently using core accesses.
Page 173: Dma Access
External Port DMA Access Listing 3-3 shows an example of external port DMA using read optimization. Listing 3-3. EPDMA With Read Optimization ustat1=dm(SDCTL); bit set ustat1 SDROPT|SDMODIFY2; dm(SDCTL)=ustat1; nop; r0=DFLSH; dm(DMAC1)=r0; r0=intmem; dm(IIEP1)=r0; r0=2; dm(IMEP1)=r0; r0=N; dm(ICEP1)=r0; r0=2; dm(EMEP1)=r0; r0=extmem; dm(EIEP1)=r0;...
Page 174: Self-Refresh Mode
SDRAM Controller (ADSP-2147x/ADSP-2148x) Self-Refresh Mode This mode causes refresh operations to be performed internally by the SDRAM, without any external control. This means that the SDC does not generate any auto-refresh cycles while the SDRAM is in self-refresh mode. Self-refresh entry—Self-refresh mode is enabled by writing a 1 to the bit of the SDRAM memory control register ( ).
Page 175: Forcing Sdram Commands
External Port The following steps are required when using self-refresh mode. 1. Set the bit to enter self-refresh mode SDSRF 2. Poll the bit in the SDRAM status register ( ) to deter- SDSRA SDSTAT mine if the SDRAM has already entered self-refresh mode. 3.
Page 176: Force Load Mode Register
DDR2 DRAM Controller (ADSP-2146x) Force Load Mode Register Programs can use the Force LMR command by setting bit 22 (=1) in the register. This command is preceded by a precharge all (if banks not SDCTL idle) followed by a mode register write. The Force LMR bit allows changes to the register based settings dur- MODE...
Page 177 External Port • Supports 4 and 8 bank DDR2 devices • Variable memory address map (bank or page interleaving) • Supports a maximum of 2G bit through the external DDR2 bank (64M words x 32) • Supports up to 254M words of DDR2 memory •...
Page 178: Pin Descriptions
DDR2 DRAM Controller (ADSP-2146x) • Supports dual data instruction type 1 • Parallel access between DDR2 and AMI possible (no multiplexed pins) Pin Descriptions The pins used by the external memory interface are described in the ADSP-2146x SHARC Processor Data Sheet. Additional information on pin multiplexing can be found in “Pin Descriptions”...
Page 179 External Port It should be noted that the DDR2 DLL acts as an interface for only the signals mentioned above and the clock output ( ) to the DDR2, it DDR2_CLK does not operate on the and command lines ( DDR2_ADDR DDR_CS DDR2_RAS...
Page 180 DDR2 DRAM Controller (ADSP-2146x) and falling edges of the signal. The read data is captured by the DDR2_DQS DDR2 DLL using a delayed that is phase shifted by approximately 90 degrees for the positive edge data and by approximately 90 degrees for the negative edge data.
Page 181: Ddr2 Commands
External Port For read commands, there is a latency from the start of the read command to the availability of data from the DDR2, equal to the CAS latency. This latency is always present for any single read transfer. Subsequent reads do not have latency.
Page 182: Load Extended Mode Register
DDR2 DRAM Controller (ADSP-2146x) • Bits 6–4 – CAS latency, programmable in the register DDR2CTL0 • Bit 7 – Always 0 • Bit 8 – reset DLL (DDR2 device) • Bits 11–9 = Reserved • Bits 13–12 = Always zero •...
Page 183: Load Extended Mode Register 2
External Port 6. Bit 10 – Differential enable/disable DDR2_DQS 7. Bit 12 – Output buffer enable/disable 8. Bits 15–14 = 01 for EMR1 The command can also be triggered by setting the bit in the FEMR register. DDR2CTL0 Load Extended Mode Register 2 Values written into the register are loaded into the register...
Page 184 DDR2 DRAM Controller (ADSP-2146x) different internal banks. For 8 banked devices, the controller does follow the t specification. Precharge This command is executed by the controller if the address to be accessed falls in a different page in the same external bank and the same internal bank.
Page 185 External Port Each subsequent data-out appears on the pin in phase with the DDR2_DATA signal in a source synchronous manner. DDR2_DQS The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the mode register (MR), similar to the existing SDRAM. The AL is defined by the register.
Page 186 DDR2 DRAM Controller (ADSP-2146x) The subsequent burst bit data are issued on successive edges of DDR2_DQS until the burst length is completed. When the burst has finished, any additional data supplied to the pins is ignored. The DDR2_DATA DDR2_DATA signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (WR).
Page 187 External Port Self-Refresh Entry Self-refresh mode causes refresh operations to be performed internally by the DDR2 controller, without any external control. This means that the controller does not generate any auto refresh cycles while it is in self-refresh mode. The self-refresh entry command is performed by writ- ing a 1 to the bit of the memory control register ( ).
Page 188 DDR2 DRAM Controller (ADSP-2146x) mode programs need to consider if this occurs during a read or write. If exiting during a read, additional latency occurs because the on-chip DLL needs to be locked again. When an internal access occurs (or with careful software control) the bit is set in register and the controller: SREF_EXIT...
Page 189 External Port meeting the required timing specifications, pulls down the signal. DDR2CKE If an internal access is pending, the controller delays entering the power-down mode until it completes the pending DDR2 access and any subsequent pending access requests. • = 0 No effect. DIS_DDR2CKE •...
Page 190 DDR2 DRAM Controller (ADSP-2146x) No Operation/Command Inhibit The no operation (NOP) command to the DDR2 has no effect on opera- tions currently in progress. When the controller is actively accessing the DDR2 but needs to insert additional commands with no effect, the NOP command is given.
Page 191 External Port Bank Unused Row Address Column Address Address Figure 3-14. Core Address Mapping to Row, Column Addresses (Page) One advantage of the page interleaving is that the effective page size is up to four pages (assuming four banks activated) and all the addresses are sequential.
Page 192 DDR2 DRAM Controller (ADSP-2146x) bits in the register. The bank address width is three bits as DDR2CTL0 shown in Table 3-11. Table 3-11. External Memory Address Bank Decoding IA[27] IA[26] External Bank Bank 0 Bank 1 Bank 2 Bank 3 Row Address Width (DDR2RAW).
Page 193 External Port For example, if the processor core requests address 0x20 0000 for a 32-bit access, thecontroller performs two 16-bit accesses at 0x40 0000 and 0x40 0001, using MS0 to get one 32-bit data word.  bit must always be set. X16DE Address Map Tables The row address and column address mappings for 16-bit addresses are...
Page 194 DDR2 DRAM Controller (ADSP-2146x) Table 3-12. 16-bit Address Mapping (8 Banks, Page Interleaving) (Cont’d) SHARC Pin Column Address Row Address Bank Address DDR2 Pin DDR2_ADDR[4] IA[3] IA[16] A[4] DDR2_ADDR[3] IA[2] IA[15] A[3] DDR2_ADDR[2] IA[1] IA[14] A[2] DDR2_ADDR[1] IA[0] IA[13] A[1] DDR2_ADDR[0] IA[12] A[0]...
Page 195 External Port Table 3-13. 16-bit Address Mapping (4 Banks, Page Interleaving) (Cont’d) SHARC Pin Column Address Row Address Bank Address DDR2 Pin DDR2_ADDR[1] IA[0] IA[13] A[1] DDR2_ADDR[0] IA[12] A[0] Table 3-14 shows = 1, = 100 (12), = 10 DDR2ADDRMODE DDR2RAW DDR2CAW (10),...
Page 196 DDR2 DRAM Controller (ADSP-2146x) Table 3-15 shows = 1, = 100 (12), = 11 DDR2ADDRMODE DDR2RAW DDR2CAW (11), = 01(four banks). DDR2BC Table 3-15. 16-bit Address Mapping (4 Banks, Bank Interleaving) SHARC Pin Column Address Row Address Bank Address DDR2 Pin DDR2_BA1 IA[23] BA[1]...
Page 197 External Port The delay (in number of cycles) desired between consecutive DDR2_CLKx refresh counter time-outs must be written to the field. A refresh RDIV counter time-out triggers an auto-refresh command to the external DDR2 bank. Write the value to the register before the DDR2 RDIV DDR2RRC...
Page 198 DDR2 DRAM Controller (ADSP-2146x) = 9 cycles = 3 cycles The equation for yields: RDIV –6 = (200 × 10 × 7.8 × 10 ) – (9 + 3) = 1548 clock cycles. RDIV This means is 0x614 and the register bits 13–0 should be RDIV DDR2RRC...
Page 199 External Port (hardware reset) immediately after reset, timing parameter cannot be met, causing data loss. The DDR2 device must be re-initialized and the DDR2 DLL must be re locked to use the DDR2 again.  Running reset ( pin as an input) does not reset the DDR2 RESETOUT controller.
Page 200 DDR2 DRAM Controller (ADSP-2146x) 7. Issue a load MR command. Wait t period. Also trigger a coun- ter (200 cycle counter)—any read command is issued only after this counter expires. 8. Issue a precharge all command. Wait t period. 9. Issue two or more auto refresh commands, with a t period in between each command.
Page 201 External Port Internal DDR2 Bank Access The following sections describe the different scenarios for DDR2 bank access. Single Bank Access The DDR2 controller keeps only one page open at a time if all subsequent accesses are to the same row or another row in the same bank. Multibank Access The processors are capable of supporting multibank operation, thus taking advantage of the DDR2 architecture.
Page 202 DDR2 DRAM Controller (ADSP-2146x) Access to page x Access to page x Bank A Bank A Access to page y Access to page y Bank B Bank B Access to page x Bank C Bank C Access to page y Bank D Bank D Single bank access...
Page 203 External Port DDR2_CLKx DDR2_CLKx/ COMMAND READ READ READ READ BA0, BA1, Bank Bank Bank Bank Bank Bank Bank Bank Bank t RDD(min) t RDD(min) t RDD(min) t RDD(min) Figure 3-17. Bank Activation for a 8 Banked Device  Multibank access reduces precharge and activation cycles by map- ping opcode/data among different internal DDR2 banks driven by the ( ) pins and external memory selects (...
Page 204 DDR2 DRAM Controller (ADSP-2146x) 0x200A00 logical start address int bankF 0x200BFF logical end address int bankF 0x200C00 logical start address int bankG 0x200DFF logical end address int bankG 0x200E00 logical start address int bankH 0x201000 logical end address int bankH Bank Interleaving (DDR2ADDRMODE bit = 1): 0x200000 logical start address int bankA 0x2001FF logical end address int bankA...
Page 205 External Port • t (row refresh cycle). Required delay time to refresh a single row. This parameter is fixed to t cycles. • t (exit self-refresh with non-read). Required delay to exit the XSNR self-refresh mode with a non read command. This parameter is fixed to t + 4 cycles.
Page 206 DDR2 DRAM Controller (ADSP-2146x) • 2 x 8-bit/page 1k words • 4 x 4-bit/page 2k words The DDR2’s page size is used to determine the system you select. All three systems have the same external bank size, but different page sizes. Note that larger page sizes, allow higher performance but larger page sizes require more complex hardware layouts.
Page 207 External Port  For SIMD accesses, if optimization is enabled and the modifier is set to 2 (even if the modifier is changed, it remains at 2). The throughput is at maximum if optimization is enabled for sequential accesses. But in the case of non sequential accesses, throughput is affected by enabling optimization.
Page 208 DDR2 DRAM Controller (ADSP-2146x) Listing 3-4. Maximum Throughput Using Sequential Reads ustat1=dm(DDR2CTL0); bit set ustat1 DDR2OPT|DDR2MODIFY1; dm(DDR2CTL0)=ustat1; nop; I0 = DDR2_addr; M0 = 1; Lcntr = 1024, do(PC,1) until lce; R0 = R0 + R1, R0 = dm (I0, M0); The example shows read optimization can be used efficiently using core accesses.
Page 209 External Port Listing 3-6. EPDMA With Read Optimization ustat1=dm(DDR2CTL0); bit set ustat1 DDROPT|DDRMODIFY2; dm(SDCTL)=ustat1; nop; r0=DFLSH; dm(DMAC1)=r0; r0=intmem; dm(IIEP1)=r0; r0=2; dm(IMEP1)=r0; r0=N; dm(ICEP1)=r0; r0=2; dm(EMEP1)=r0; r0=extmem; dm(EIEP1)=r0; r0=DEN; dm(DMAC1)=r0; Notes on Read Optimization The core and the DMA engine take advantage of the major improvements during reads using read optimization.
Page 210 DDR2 DRAM Controller (ADSP-2146x) is currently underway. The DDR2 remains in self-refresh mode for at least and until an internal access (read/write) to DDR2 space occurs.  The self-refresh entry command does automatically disable the DDR2 memory DLL. Therefore its release command (exit) requires additional stall cycles until the DLL has re-locked.
Page 211 External Port DDR2 access occurs and the DDR2 exits from self-refresh mode.  The minimum time between a subsequent self-refresh entry and exit command is the t cycle. If a self-refresh request is issued during any external port DMA, the DDR2 controller grants the request with the t cycle and continues DMA operation afterwards.
Page 212 DDR2 DRAM Controller (ADSP-2146x) Additive Latency Posted CAS operation is supported to make the command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command (or any time during the RAS-CAS-delay time, t , period).
Page 213 External Port Force Load Mode Register Programs can use the Force LMR command by setting bit 22 (=1) in the register. The Force LMR bit allows changes to the register DDR2CTL0 MODE based settings during runtime. These settings include bit 22 (=1) for MR command (settings register).
Page 214 Data Transfer Data Transfer The AMI can access data from both the core and through DMA. The fol- lowing sections describe these options. Data Buffers The asynchronous memory interface has two 1 deep data buffers, one each for the transmit and receive operations. These are described in the sections that follow.
Page 215 External Port Whenever the buffer is empty, the DMA controller or a direct AMITX access from the processor core can write new data into the AMI. If the reg- ister is full, further writes from the core (or DMA controller) are stalled. ...
Page 216: Conditional Instructions
Data Transfer Conditional Instructions On the SHARC processors, almost all instruction types can be condi- tional. Access to external data based on a conditional instructions are allowed. For example: r10=pass r9; If EQ r4=r2+r3, r2=dm(i6,m6); The instruction is only executed if the condition is true. SIMD Access The SHARC processor supports SIMD data access from external DDR2 memory.
Page 217: Ddr2
External Port The first access does the explicit 32-bit access (which results in the physi- cal space in 2x16-bit words) while the 2nd 32-bit access does the implicit transfer. In total there are four read or write commands as shown in Table 3-16.
Page 218: External Instruction Fetch
Data Transfer  Bursts are not divisible. During reads, all DDR2 data are received and on-chip masked by the DDR2 controller. For single write access in SISD mode, the 3rd and 4th data needs to be masked. The data masking ( signal) is only performed during DDR2_DM1-0 write operations as shown in...
Page 219: Fetching Isa Instructions From External Memory
External Port selected boot mode. However for all boot modes except the reserved boot mode, the default bit setting is 1 ( IIVT SYSCTL Therefore, if instruction fetch from external memory is desired upon reset, the program needs to set up the appropriate interrupt vector tables in internal memory as part of the boot-up code before beginning to fetch these instructions.
Page 220: Instruction Packing
Data Transfer Instruction Packing Any address produced by the sequencer which falls in external memory is first translated into the physical address in external memory based on the actual data bus width of external memory as shown in Figure 3-18. The controller completes the required number of accesses from consecu- tive locations for returning a 48-bit word instructions.
Page 221 External Port Table 3-19. Logical Versus Physical Address Mapping, 16-Bit AMI Logical ISA Normal Word Physical Address, External Bus Data15–0 Address, Program Sequencer 0x20 0000 0x60 0000 Instr0[15:0] 0x60 0001 Instr0[31:16] 0x60 0002 Instr0[47:32] 0x20 0001 0x60 0003 Instr1[15:0] 0x60 0004 Instr1[31:16] 0x60 0005 Instr1[47:32]...
Page 222: 8-Bit Instruction Storage And Packing
Data Transfer 8-Bit Instruction Storage and Packing Table 3-20, the logical to physical translation is a multiplication by a factor of 6 and N = 0xAAAA9. Therefore, the 8-bit wide AMI supports 0.7 million instructions. Table 3-20. Logical Versus Physical Address Mapping, 8-Bit AMI Logical ISA Normal Word Physical Address, External Bus...
Page 223: Mixing Instructions And Data In External Bank 0
External Port Mixing Instructions and Data in External Bank 0 It is possible to store both 48-bit instructions as well as 16-bit data in external memory bank 0. However, care must be taken while specifying the proper starting addresses if 48-bit instructions are stored or interleaved with 16-bit data in the same memory bank.
Page 224: Writing Instructions To External Memory
Data Transfer Table 3-22 provides addressing for various sizes of SDRAM memory. Table 3-22. Translation of Logical to Physical Addressing for SDRAM DDR2 Device Physical Address Range Mapped to Mapping Between External Port Memory Device Address Range and Memory Device 32 Mb (x16) 0x60 0000 –...
Page 225: Instruction Cache
External Port Table 3-23. Booting Instructions Into External Memory Sequencer Feych Normal Word Normal Word Data Address Address 0x20 0001 0x30 0002 Instr/Fetch1 [47:16] 0x30 0003 Instr/Fetch2 [31:0] 0x20 0002 0x30 0004 Instr/Fetch3 [15:0] Instr/Fetch2 [47:32] 0x30 0005 Instr/Fetch3 [47:16] Instruction Cache To circumvent the relative difference in clock domains between the core and external memory interface (1:2 in the best case) and enable faster exe-...
Page 226 Data Transfer VALID INSTRUCTIONS ADDRESSES ADDRESSES BITS (23-4) BITS (3-0) ENTRY 0 0000 ENTRY 1 ENTRY 0 0001 ENTRY 1 ENTRY 0 0010 ENTRY 1 ENTRY 0 1101 ENTRY 1 ENTRY 0 1110 ENTRY 1 ENTRY 0 1111 ENTRY 1 Figure 3-19.
Page 227 External Port This context-dependent caching preserves the cache performance of the traditional SHARC conflict cache as well as significantly improving pro- gram instruction throughput for repetitive instructions such as those inside loops when executing from external memory. Analyses of typical application code examples have shown that this 32-entry instruction cache improves execution throughput by 50-80% over not having this cache.
Page 228: Fetching Visa Instructions From External Memory
Data Transfer minimum of 48 cycles over a 16-bit wide external bus (excluding any con- flicts for data operand fetches). However, with the presence of the instruction cache, and assuming that the execution is from external SDRAM, and that the instructions are on the same SDRAM page, the number of cycles is reduced to 17 over a 16-bit wide external bus, and either 15 cycles or 16 cycles over a 32-bit wide bus (depending on whether instruction 1 begins on an even 32-bit address, or odd 32-bit address).
Page 229 External Port in external memory, the external memory address range has been divided into two ranges: • Normal word – 0x20 0000 to 0x5F FFFF • Short word – 0x60 0000 to 0xFF FFFF When the processor accesses any instruction from the external normal word space, the instruction is deemed to have the traditional SHARC instruction encoding.
Page 230: External Port Dma
External Port DMA PHYSICAL ADDRESS (TRANSLATED BY INTERFACE FOR X16 DEVICE) 0x40 0000 LOGICAL ADDRESS (GENERATED BY SEQUENCER) 0x60 0000 0x80 0000 0x20 0000 ISA (NW) OPERATION 0x5F FFFF 0x60 0000 0xFF FFFF VISA (SW) OPERATION 0xFF FFFF 0x11F FFFF Figure 3-20.
Page 231 External Port up DMA transfers, see “General Procedure for Configuring DMA” on page 2-51. The registers that control external port DMA are described Table 3-24. Table 3-24. DMA Parameter Registers Register Description Comment IIEPx Internal Index Internal Start Address. For delay line DMA, it serves as the delay line write index;...
Page 232: Operating Modes
External Port DMA Table 3-25. Enhanced DMA Parameter Registers (Cont’d) Register Description Comment TCEPx Tap Count Holds the length of the tap list (the number of taps for delay line DMA, scatter/gather DMA). TPEPx Tap List Pointer Holds address of an array in internal memory which holds offsets to be used when accessing delay line DMA in external memory.
Page 233: Standard Dma
External Port Standard DMA This DMA type resembles the traditional DMA type to initialize the dif- ferent internal and external parameters (index, modify and count) registers and configuration of the DMA control registers. Note that the parameter register (read only) is a copy of the reg- ECEP ICEP...
Page 234 External Port DMA SOURCE BUFFER DESTINATION BUFFER DESTINATION BASE ADDRESS (EBEP) DESTINATION INDEX (IIEP) BUFFER LENGTH (ELEP) SOURCE INDEX (IIEP) Figure 3-22. Circular Buffering Write DMA SOURCE BUFFER DESTINATION BUFFER SOURCE INDEX (EIEP) SOURCE BASE ADDRESS (EBEP) BUFFER LENGTH (ELEP) DESTINATION INDEX (IIEP) Figure 3-23.
Page 235 External Port Bit 20 ( ) bit of the external port chain pointer register ( CPDR CPEPx changes the data flow direction. If is cleared (=0) writes to internal CPDR memory are performed, if is set (=1), internal memory reads are per- CPDR formed.
Page 236: Scatter/Gather Dma
External Port DMA  If chaining is enabled with the bit set then the bit has OFCEN TRAN no effect, and direction is determined by the bit in the CPDR CPEP register. Scatter/Gather DMA The purpose of scatter/gather DMA (Table 3-26, Figure 3-24 through...
Page 237 External Port the internal count register ( ), and is the same for every tap. The ICEPx read/write pointer in external index register ( ) serves as the index EIEPx address for these read/writes. TL[N] is the first tap list entry in the internal memory as pointed by the , the tap list pointer.
Page 238 External Port DMA TAP LIST BUFFER TAP LIST POINTER (TPEP) OFFSET1 OFFSET2 OFFSET3 DESTINATION INDEX (IIEP) SOURCE INDEX (EIEP) EIEP + OFFSET1 EIEP + OFFSET2 SOURCE BUFFER EIEP + OFFSET3 DESTINATION BUFFER Figure 3-24. Scatter DMA (Writes) 3-108 ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 239 External Port TAP LIST BUFFER TAP LIST POINTER (TPEP) OFFSET1 OFFSET2 OFFSET3 DESTINATION SOURCE INDEX (EIEP) INDEX (IIEP) EIEP + OFFSET1 SOURCE BASE (EBEP) EIEP + OFFSET2 DESTINATION BUFFER EIEP + OFFSET3 SOURCE BUFFER Figure 3-25. Gather DMA (Reads) ADSP-214xx SHARC Processor Hardware Reference 3-109 www.BDTIC.com/ADI...
Page 240 External Port DMA TAP LIST BUFFER TAP LIST POINTER (TPEP) SOURCE INDEX (EIEP) DESTINATION INDEX (IIEP) EIEP + 20 SOURCE BASE (EBEP) EIEP + 4 EIEP + 28 EIEP + 12 EIEP + 36 SOURCE BUFFER DESTINATION BUFFER Figure 3-26. Circular Buffering Scatter DMA (Writes) 3-110 ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 241: Delay Line Dma
External Port TAP LIST BUFFER TAP LIST POINTER (TPEP) DESTINATION INDEX (IIEP) SOURCE INDEX (EIEP) EIEP + 20 SOURCE BASE (EBEP) EIEP + 4 EIEP + 28 EIEP + 12 EIEP + 36 SOURCE BUFFER DESTINATION BUFFER Figure 3-27. Circular Gather DMA (Reads) Delay Line DMA Delay line DMA is used to support reads and writes to external delay line buffers with limited core interaction.
Page 242: External Address Calculation For Reads
External Port DMA single reads from each TAP are shown for simplicity and block reads are default, depending on the count specified in the register. RCEP 1. Writes to external memory. The number of writes is determined by register. The data is fetched from the register and the ICEP IIEP...
Page 243 External Port EXTERNAL MEMORY (DELAY LINE) INTERNAL MEMORY IIEP 0xC2000 0xAAAAAA C000 IMEP 0xBBBBBB C001 ICEP 0xCCCCCC C002 EIEP 0x0009 0xDDDDDD ..DELAY-LINE EMEP 0xEEEEEE TAP LIS SAMPLE (N-M) EBEP 0x00000 0xFFFFFF ELEP 0x121212 0x343434 C000 RIEP 0xC1000 0x343434 0XEEEEEE C001 RCEP...
Page 244: Interrupts
Interrupts Table 3-27. External Read Index Calculation Delay Line DMA Equation Result EIEP + TL[N] First read address for tap N EIEP + TL[N] + 1 × RMEP Second read address for tap N EIEP + TL[N] + 2 × RMEP Third read address for tap N EIEP + TL[N] + RCEP ×...
Page 245: Access Completion
External Port Access Completion This is the default mode of interrupt generation where the DMA complete interrupt is generated when accesses are completed. • For external write DMA, the DMA complete interrupt is generated only after external writes on the DMA external interface are done. •...
Page 246: External Port Throughput
External Port Throughput completion or access completion. The following also effect interrupt generation. • For standard chained DMA, if the bit is cleared (= 0), the DMA complete interrupt is generated only after the entire chained DMA access is complete. If the bit is set (= 1), then a DMA interrupt is generated for each TCB.
Page 247: Ami Data Throughput
External Port AMI Data Throughput The AMI data throughput is shown in Table 3-29. Table 3-29. Read/Write Throughput 8-Bit I/O 16-Bit I/O Access Write 32-bit word per 12 cycles 32-bit word per 6 cycles Read 32-bit word per 12 cycles 32-bit word per 6 cycles 1 Throughput for minimum wait states of 2 with no idle and hold cycles.
Page 248: Ddr2 Throughput
External Port Throughput DDR2 Throughput The following sections provide information needed to configure the DDR2 interface for the desired throughput. DMA Throughput Table 3-31 provides approximate throughput information with the pro- cessor core running at 400 MHz for DMA-driven reads and writes of external DDR2 memory.
Page 249: External Instruction Fetch Throughput
External Port external DDR2 memory. The throughput numbers shown are measured by running a loop of 1024 read/writes (512 in case of SIMD reads/writes). For the analysis, 16-bit DDR2 is used (t =10, t =2, t =3, t =3, t =1, t =3, t =8, CL=4, AL=4, t...
Page 250 Effect Latency Table 3-33 illustrates the performance of code execution depending on different access types. Table 3-33. Core Throughput Access Data Page Throughput per Throughput per Width SDCLK (CL = 2) SDCLK (CL = 3) Sequential uninter- Same 2 instructions per 6 2 instructions per 6 rupted reads cycles*...
Page 251: Write Effect Latency
External Port Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference. Programming Models The following sections provide information on the various programming models that are used through the external port interface. External Port The section describes software programming steps required for the suc- cessful operation of the external port.
Page 252: Chained Dma
Programming Models 4. If scatter/gather DMA is desired, program additional writes to the registers. TCEP TPEP 5. Enable DMA using the bit, and set the transfer direction DMAEN using the bit in the registers. If scatter/gather DMA is TRAN DMACx desired, set the bit.
Page 253: Delay Line Dma
External Port 4. If circular buffering is needed, use the corresponding TCB storage. 5. Enable DMA using the , bit, set chaining using the bit. DMAEN CHEN If circular buffering is required, set the bit in the regis- CBEN DMACx ters.
Page 254: Disabling And Re-Enabling Dma
Programming Models interrupt is generated at the end of each delay line DMA block or at the end of entire chained DMA, depending on the bit setting.  When delay line DMA is enabled with chaining, all the chained DMA blocks follow the delay line DMA access procedure. It is not possible to mix normal DMA with delay line DMA in chained DMA.
Page 255: Ami Initialization
External Port 3. For a chained DMA, new TCB loading can be inhibited by clearing bit while keeping all other control bits the same. The new CHEN TCB is loaded once bit is re-enabled. The TCB load which CHEN was happening when was cleared will complete.
Page 256: Sdram Controller
Programming Models SDRAM Controller This section describes software programming steps required for the suc- cessful operation of the SDC. Power-Up Sequence After reset, the is running with the default PLL settings. However, SDCLK the SDC must be configured and initialized. In order to set up the SDC and start the SDRAM power-up sequence for the SDRAMs, use the fol- lowing procedure.
Page 257: Output Clock Generator Programming Model
External Port Output Clock Generator Programming Model The following non VCO programming sequence may be used to change the output generator clock and the core-to-peripheral clock ratio (for example the SDRAM clock). Note that if your program is only changing the PLL output divider, programs do not need to wait 4096 cycles CLKIN...
Page 258: Changing The Vco Clock During Runtime
Programming Models 4. Self refresh mode-no activities on all SDRAM signals (clock optional). 5. Clear the bit to re-enable (optional). DSDCTL SDCLK 6. SDRAM access releases controller from self-refresh mode. Changing the VCO Clock During Runtime In previous SHARC models, only a hardware reset initiated another SDRAM power-up sequence.
Page 259: Ddr2 Controller
External Port 3. Execute the desired PLL programming sequence. (For more infor- mation, see “PLL Start-Up” on page 22-9.) 4. Wait 4096 cycles ( asserted) which indicates the CLKIN RESETOUT PLL has settled to the new frequency. 5. Reprogram the SDRAM registers ( ) with values appro- SDRRC SDCTL...
Page 260: Frequency Change In Precharge Power-Down Mode
Programming Models 5. DLL in reset starts new locking event. Wait for the DLL to lock to the new frequency. Note DLL locking time depending on the CCLK ratio is: DDR2_CLK • 1:2 – 3000 cycles CCLK • 1:3 – 7500 cycles CCLK •...
Page 261: External Instruction Fetch
External Port frequency change requires self-refresh mode. The DDR2 DDR2 input core to DDR2 clock ratio change can be made under following condition: 1. The ODT must be turned off. 2. Put the DDR2 DDR2 in precharge power down mode ( DDR2CKE pin goes low).
Page 262: Ami Configuration
Programming Models AMI Configuration For instruction fetch, the original (logical) address is multiplied by 3/2 and this address is translated depending on the bus width and PKDIS setting. 1. Assign external bank0 to AMI in the register (default). EPCTL 2. Wait at least 8 cycles (effect latency).
Page 263 External Port 4. A one cycle stall is generated whenever an instruction that contains a conditional external memory access is in the decode stage, where the evaluation of the condition is dependent on the outcome of the previous instruction in address stage. It applies to all kinds of con- ditions except for conditions based on FLAG status.
Page 264 Programming Models 3-134 ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 265: Link Ports-Adsp-2146X
4 LINK PORTS—ADSP-2146X The ADSP-2146x processors have two 8-bit wide link ports, which can connect to another processor or peripheral link ports. The link ports allow a variety of interconnection schemes to I/O peripheral devices as well as co-processing and multiprocessing schemes. The port specifications are shown in Table 4-1.
Page 266: Features
Features Table 4-1. Link Port Specifications (Cont’d) Feature Link Port1–0 Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Yes (Link Port 0) Local Memory Clock Operation LCLK Features These bidirectional ports have eight data lines, an acknowledge line, and a clock line.
Page 267: Pin Descriptions
Link Ports—ADSP-2146x • Include programmable clock and acknowledge controls for link port transfers. Each link port has its own dedicated DMA channel. • Provide high-speed, point-to-point data transfers to other proces- sors, allowing differing types of interconnections between multiple DSPs. Pin Descriptions The pins associated with each link port are described in the ADSP-2146x data sheet.
Page 268: Clocking
Clocking Status Registers (LSTATx). Programs can see several aspects of link port operation using the status registers. These include bus status, buffer status, receive and transmit status, and errors. Clocking The link port clock is derived from the clock out generator based on the linkport to core clock ratio.
Page 269: Architecture
Link Ports—ADSP-2146x Architecture Figure 4-2 shows the architecture of the link ports. LACKx LCLKx LDATx7-0 LTRAN TRANSMIT RECEIVE CONTROL SHIFT SHIFT STATUS BUFFER REGISTER TRANSMIT RECEIVE BUFFER BUFFER (2 DEEP) (2 DEEP) PM/DM DATA BUS IOD BUS Figure 4-2. Link Port Block Diagram Protocol A link-port-transmitted word consists of 4 bytes (for a 32-bit word).
Page 270 Functional Description to drive the first byte if is deasserted. When is eventually LACKx LACKx asserted again, the transmitter drives low and begins transmission of LCLKx the next word. If the transmit buffer is empty, remains low until the LCLKx buffer is refilled, regardless of the state of LACKx LXCLK...
Page 271: Intercommunication
Link Ports—ADSP-2146x 5. Receiver accepts the remaining word even if is deasserted. The LACK transmitter does not send the following word. 6. Transmit data for next word is held until is asserted. LACK The receive buffer may fill if a higher priority DMA, core I/O processor register access, or chain loading operation is occurring.
Page 272 Functional Description  Unlike older SHARC processors that have link ports, the ADSP-2146x processors do not have an internal pull-down resis- tor. Because of this there is no bit available to disable the PDRDE internal pull-down and an external pull-down (20K Ohms) is requ- ried on the signals.
Page 273 Link Ports—ADSP-2146x LCLKx DRIVEN BY TRANSMITTER LCLKx STAYS HIGH IF LA SAMPLED LOW ON PREV LCLKx FALLING EDGE LACKx DRIVEN BY RECEIVER LACKx MAY DEASSERT AFTER BYTE 0 TRANSMITTER SAMPLES LACKx HERE TO DECIDE WHETHER TO TRANSMIT NEXT WORD LDAT7-0 BYTE 3 BYTE 0 BYTE 1...
Page 274: Self-Synchronization
Functional Description Self-Synchronization The link ports are designed to allow long distance connections to be made between the driver and the receiver. This is possible because the links are self-synchronizing—the clock and data are transmitted together. Only rel- ative delay, not absolute delay between clock and data is relevant. In addition, the signal inhibits transmission of the next word, not of LACKx...
Page 275: Example Token Passing
Link Ports—ADSP-2146x Example Token Passing When two ADSP-2146x processors communicate using a link port only one can be the transmitter or receiver. Token passing is a protocol that assists the DSPs alternate control. Figure 4-8 shows a flow chart of the token passing process.
Page 276 Functional Description ORIGINAL SLAVE ORIGINAL MASTER DMA TRANSFER COMPLETE DMA TRANSFER COMPLETE LTRQ INTERRUPT ENABLED LINK PORT CORE Rx ENABLED LACK ASSERTION CAUSES LTRQ INTERRUPT LINK PORT Tx NON DMA ENABLED READ RECEIVE BUFFER SEND TRW 4 TIMES TO FILL LINK PORT FIFOS ON BOTH SIDES TEST FOR TRW CHECK LCTL FOR SLAVE READ OF TRW...
Page 277: Data Transfer
Link Ports—ADSP-2146x The following is a list of the areas of concern when a program implements a software protocol scheme for token passing: • The program must make sure that both link ports are not enabled to transmit at the same time. In the event that this occurs, data may be transmitted and lost due to the fact that neither link port is driving .
Page 278: Transmit Buffer
Data Transfer buffers consist of a 2 deep buffer and a shift register. The registers read from or write to internal memory under DMA or processor core control. Transmit Buffer In the transmit path, the buffer is used to accept core data or DMA data from internal memory.
Page 279: Buffer Status
Link Ports—ADSP-2146x Buffer Status The entire receive and transmit path form a 3-stage FIFO. Two writes/reads can occur to the transmit/receive buffer by the core or DMA before it signals a full/empty condition. Full/empty status for the link buf- fer is shown by the bits in the register.
Page 280: Dma Transfers
Interrupts DMA Transfers Each link port supports a DMA channel.  Note that the link ports do not support internal to internal mem- ory transfers like previous SHARCs (no link assignment register). If internal to internal memory transfers are required, refer to “External Port DMA”...
Page 281: Interrupt Sources
Link Ports—ADSP-2146x Interrupt Sources Five types of interrupts are dedicated to link ports. 1. A DMA channel interrupt is generated when a DMA block transfer through the link port with DMA enabled completes. 2. A DMA channel interrupt is generated when DMA for the link buffer channel is disabled and the buffer is not full or the buffer is not empty.
Page 282: Access Completion
Interrupts corresponding status register ( ). Reading the status register clears LSTATx the interrupt bits. Read of the status register when an interrupt occurs causes the core to hang till the interrupt bits are set in the status register. Otherwise simultaneous read of the status register and updating of the sta- tus register will result in loss of information.
Page 283: Dma Access
Link Ports—ADSP-2146x DMA Access A link port interrupt is generated when the DMA operation is done— when the block transfer has completed and the DMA count register is zero. One way programs can use this interrupt is to send additional control information at the end of a block transfer.
Page 284: Service Request Interrupts
Interrupts If the DMA is disabled but the associated link buffer is enabled, then a maskable interrupt is generated whenever a receive buffer is not empty or when a transmit buffer is not full. This interrupt is the same interrupt vec- tor associated with the completion of the DMA block transfers.
Page 285: Debug Features
Link Ports—ADSP-2146x LSRs are gated by mask bits and then ORed together to generate the link service request interrupt. The interrupt requests may be masked by LSRQ the receive ( ) or transmit ( ) bits of the register. LRRQ_MSK LTRQ_MSK LCTLx When the mask bit is set, the interrupt is allowed to pass into the inter-...
Page 286: Buffer Hang Disable (Bhd)
Effect Latency Buffer Hang Disable (BHD) A buffer hang disable ( ) bit has been provided in the control register ). Setting this bit to 1 prevents the core from hanging when a read LPCTLx from an empty receive buffer or a write to a full transmit buffer is attempted.
Page 287: Changing The Link Port Clock
Link Ports—ADSP-2146x Changing the Link Port Clock The following programming sequence may be used to change the core-to-link port clock ratio only. Note that this procedure changes only the PLL output divider. Therefore programs do not need to wait 4096 cycles (required only if the PLL multiplier or the bit is CLKIN...
Page 288: Receive Dma
Programming Model Receive DMA The following is the sequence that occurs when an external device trans- fers a block of data into the processor’s internal memory using a link port.  Note that the link ports do not support internal to internal mem- ory transfers like previous SHARCs.
Page 289 Link Ports—ADSP-2146x 2. The processor enables the link port by setting the bit and enables the link port DMA by setting the bit in the LCTLx LDEN register. Because this is a transmit, setting automatically LDEN asserts an internal DMA request. 3.
Page 290 Programming Model 4-26 ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 291: Memory-To-Memory Port Dma
5 MEMORY-TO-MEMORY PORT DMA Table 5-1 shows the memory-to-memory DMA port specifications. Table 5-1. MTM Port Specifications Feature Availability Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex...
Page 292: Features
Features Table 5-1. MTM Port Specifications (Cont’d) Feature Availability Boot Capable Local Memory Clock Operation PCLK Features The memory-to-memory port incorporates: • 2 DMA channels (read and write) • Internal to internal transfers • Data engine for DTCP applications (only for special part numbers) Note that the SHARC supports another internal to internal DMA module (external port) which does support multiples DMA modes.
Page 293: Functional Description
Memory-to-Memory Port DMA Functional Description The MTM module owns two DMA channels one for read and one for write including a data buffer which stores up to 2x32-bit data. After the DMA is configured, the read DMA channel fills the buffer with 64-bit data.
Page 294: Dma Transfer
Interrupts DMA Transfer Two DMA channels are used for memory-to-memory DMA transfers. The write DMA channel has higher priority over the read channel. The trans- fer is started by a write DMA to fill up the MTM buffer with a 2 x 32-bit word.
Page 295: Mtm Throughput
Memory-to-Memory Port DMA MTM Throughput Data throughput for internal to internal transfers is 12 cycles for PCLK 64-bit data. Effect Latency The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific). Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference.
Page 296 Programming Model ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 297: Fft/Fir/Iir Hardware Modules
6 FFT/FIR/IIR HARDWARE MODULES Finite Impulse Response (FIR) filters are frequently used in DSP applica- tions. With its high performance floating-point processing capabilities the SHARC processors are uniquely designed for FIR filtering. The SIMD SHARC core has two MAC units which provide 800 MIPS of processing speed when the processor is running at 400 MHz.
Page 298 Table 6-1. Accelerator Specifications Feature FFT/FIR/IIR Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access...
Page 299: Fft Accelerator
FFT/FIR/IIR Hardware Modules FFT Accelerator The FFT accelerator (shown in Figure 6-1) implements radix-2 complex floating-point FFT. The accelerator’s data and twiddle coefficient inter- face is designed to connect to the processor’s DMA engine (acting like a peripheral) and implements a synchronous pipeline read/write protocol with a pipeline depth of 1.
Page 300: Features
FFT Accelerator Features The following list describes the features available through the FFT accelerator. • Supports FFT sizes from 16 – 8k points all handled by DMA with no core intervention. • Computes a radix 2 decimation in time algorithm with automated bit reversal.
Page 301: Clocking
FFT/FIR/IIR Hardware Modules Control Register (FFTCTL2). Used to configure individual FFT parame- ters (such as length) and how the module process the FFT, such as data packing. MAC Status Register (FFTMACSTAT). Reports errors and status on the multiply/accumulator. DMA Status, Shadow DMA Status Registers (FFTDMASTAT, FFTSHDMASTAT).
Page 302: Data Memory
FFT Accelerator Data Memory The accelerator has a 1024 location deep, 32-bit wide data memory, orga- nized into four independent blocks. Blocks are grouped in sets of two that are used to fetch or store real and imaginary parts of data simultaneously. Fetches and stores are accomplished by ping-ponging the read and write buffers.
Page 303: Idle State
FFT/FIR/IIR Hardware Modules Resetting via a logic low to the pin resets all registers, thereby clear- RESET ing the bit. Once the processor is brought out of reset by applying FFT_RST a logic high to the pin, the FFT module goes into the idle state in RESET the next clock cycle.
Page 304: Internal Memory Storage
FFT Accelerator Internal Memory Storage This section describes the required software buffers in internal memory and the required storage model for data and coefficients using the FFT accelerator. Small FFT N<=256 To run a small FFT three buffers are required: •...
Page 305 FFT/FIR/IIR Hardware Modules Large FFT N>=256 To run a large FFT 7 buffers are required: • Input Buffer [2 × N] (packed data) • Special Buffer [2 × N] (intermediate buffer used in step 1 for verti- cal FFT and in step 2 for special product = Product of vertical buffer with special twiddles) •...
Page 306 FFT Accelerator Special coefficient buffer Re(SP_CF[0]), Im(SP_CF[0]), -Im(SP_CF[0]), Re(SP_CF[0]), Re(SP_CF[1]), Im(SP_CF[1]), -Im(SP_CF[1]), Re(SP_CF[1]), ..Re(SP_CF[N-1]), Im(SP_CF[N-1]), -Im(SP_CF[N-1]), Re(SP_CF[N-1]) (4N words). Where, = Real part of the complex coefficient Re(CF[x]) CF[x] = Imaginary part of the complex coefficient Im(CF[x]) CF[x] = Real part of special complex coefficient Re(SP_CF[x]) SP_CF[x] = Imaginary part of special complex coefficient...
Page 307: Operating Modes
FFT/FIR/IIR Hardware Modules j2π – ----------- Operating Modes The following sections describe FFT processing types and methods. Small FFT Computation (<= 256 Points) A small FFT ( = zero) can be handled completely in one step NOVER256 since the twiddles and input data stream fit in the local memories for twiddles and data.
Page 308: Example For Fft Size N=512
FFT Accelerator The final FFT result is obtained in internal memory, not local memory. Example for FFT Size N=512 This example shows a large FFT matrix of V × H = 32 × 16. Vertical FFT 1. Input coeff DMA from vertical coeff buffer[64] 2.
Page 309: Horizontal Fft
FFT/FIR/IIR Hardware Modules 3. Third iteration: a. Input coeff DMA from special coeff buffer[512] (offset = 1024) b. Input DMA from special buffer[256] (offset = 512) c. FFT computation d. Output DMA to special buffer[256] (offset = 512) 4. Fourth iteration: a.
Page 310: No Repeat Mode
FFT Accelerator No Repeat Mode If the bit = 0, after = 1 the accelerator moves from the FFT_RPT FFT_START idle state into the read state (input DMA). After the read completes, the accelerator moves into the processing state then the write state to read the results back into internal memory.
Page 311: Inverse Fft
FFT/FIR/IIR Hardware Modules Inverse FFT The inverse FFT uses the same algorithm as the forward FFT. The acceler- ator takes advantage of this fact when processing IFFTs by setting up a coefficient TCB with change of sign for the sine twiddles (FFT uses twid- dles cosine, sine, -sine, cosine, the IFFT uses cosine, -sine, sine, cosine).
Page 312 FFT Accelerator DMA Channels and TCB Structure The accelerator has two DMA channels that connect to internal memory. The channels fetch the data and coefficients from internal memory and store the results to internal memory. The DMA controller supports circu- lar buffer chain pointer DMA.
Page 313 FFT/FIR/IIR Hardware Modules One transfer control block (TCB) needs to be configured for each chan- nel. The TCB contains: • A control register value to configure the FFT parameters for each channel. • DMA parameter register values for input data. •...
Page 314 FFT Accelerator Peripheral Interrupt Control). Source bits are used to ACC0I ACC1I connect FFT interrupts to the peripheral interrupt inputs of the core. Table 6-2 povides an overview of FFT interrupts. Table 6-2. FFT Interrupt Overview Interrupt Interrupt Condition Interrupt Interrupt Default IVT Sources...
Page 315 FFT/FIR/IIR Hardware Modules status interrupt occurs programs can find the cause of the interrupt by polling the MAC status register. The MAC status bits causing the inter- rupt are sticky and cleared when the MAC status register is read. For more information, see “Multiplier Status Register (FFTMACSTAT)”...
Page 316 FFT Accelerator Vertical FFT cycles Data and coefficient reads: 2N × 2 + 2V × 2 Butterfly computes: (Vlog2V) × H Data writes: 2N × 1 Special Prod cycles Data and coefficient reads: 2N × 2 + 4N × 2 Product compute: 2 ×...
Page 317 FFT/FIR/IIR Hardware Modules Effect Latency The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific). Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference.
Page 318 FFT Accelerator LOG2HDIM FFT_RPT = 0 or 1 depending on whether FFT_CPACKIN FFT_CPACKOUT input/output data is packed into complex words or sent/received data is real or imaginary. 3. Set (=1) the bit in the register and wait for a min- FFT_RST FFTCTL1 imum of 4...
Page 319 FFT/FIR/IIR Hardware Modules 1. Configure the bits in the register to select the FFT ACCSEL PMCTL1 accelerator. 2. Program the register with: FFTCTL2 = N/16 VDIM = Log2(N) LOG2VDIM HDIM LOG2HDIM FFT_RPT = 0 or 1 depending on whether FFT_CPACKIN/FFT_CPACKOUT input/output data is packed into complex words or sent/received data is real or imaginary.
Page 320: N >= 512, No Repeat
FFT Accelerator 7. Configure a data DMA to write N complex data points from the accelerator into the output buffer (total of 2N 32-bit words). There is no need to wait until the DMA in Step 6 completes. 8. Wait until the DMA in Step 7 completes (by interrupt or polling). The computed FFTs is now in the core’s internal memory and the accelerator is in reading mode, waiting for next batch of FFTs.
Page 321: Vertical Fft Configuration
FFT/FIR/IIR Hardware Modules Vertical FFT Configuration 6. Configure a coefficient DMA to read 2V twiddle factors from the vertical coeff buffer into the accelerator (total of 2V 32-bit words) and wait until the DMA is complete (or chain DMA in Step 7). This step is not needed if twiddles are already in the coefficient memory of the accelerator.
Page 322: Horizontal Fft Configuration
FFT Accelerator Horizontal FFT Configuration 13.Once the last DMA in Step 10 completes, configure a coefficient DMA to read 2H twiddle factors from the horizontal coeff buffer into the accelerator. 14.Once the DMA in Step 12 completes, configure a data DMA (chained or via interrupt) to read 2N –...
Page 323: Debug Mode
FFT/FIR/IIR Hardware Modules 4. Program the register with: FFTCTL2 = V/16 VDIM = Log2(V) LOG2VDIM = H/16 HDIM = Log2(H) LOG2HDIM = VH/256 NOVER256 = 1. FFT_RPT 5. Program the register with: FFTCTL1 FFT_RST FFT_EN FFT_START FFT_DMAEN FFT_DEBUG For steps 6–15, see “N >= 512, No Repeat”...
Page 324: Read From Local Memory
FIR Accelerator Read from Local Memory 1. Enable FFT module using the register. PMCTL1 2. Wait at least 4 cycles. CCLK 3. Clear the bit in the register. FFT_DMAEN FFTCTL1 4. Set the bit in the register. FFT_DBG FFTCTL1 5. Write address to the register.
Page 325: Register Overview
FFT/FIR/IIR Hardware Modules Register Overview The FIR accelerator registers are described below. Power Management Control Register (PMCTL1). Used for FIR acceler- ator selection. Controls the clock power down to the module if not required. Control Registers (FIRCTLx). Used to configure the global parameters for the accelerator.
Page 326: Functional Description
FIR Accelerator Functional Description Figure 6-3 shows the block diagram of the 1024-TAP FIR hardware accel- erator. The accelerator consists of a 1024 word coefficient memory, a 1024 deep delay line for data, and four MAC units. The accelerator runs at the peripheral clock frequency ( PCLK CORE PMD/DMD...
Page 327: Compute Block
FFT/FIR/IIR Hardware Modules c. Four 32-bit floating-point and fixed-point multiplier and adder units d. One 32-bit buffer to efficiently supply data to the data path e. One 32-bit buffer to hold previous partial sum f. One 32-bit buffer to hold the output 2.
Page 328: Partial Sum Register
FIR Accelerator • 32-bit floating-point MAC operation generates 32-bit multiply results. • 32-bit fixed-point operation generates 80-bit results. COEFFICIENT DATA REGISTER REGISTER PARTIAL SUM MULT REGISTER MULT RESULT REGISTER ADDER MAC RESULT REGISTER Figure 6-4. FIR MAC Unit Partial Sum Register The partial sum register is useful for floating-point multi-iteration mode.
Page 329: Delay Line Memory
FFT/FIR/IIR Hardware Modules Delay Line Memory The accelerator has a 1024 TAP delay line to hold the data locally. The DMA controller fetches the data from internal memory and loads it into the delay line. Four read accesses can be made to the delay line simultaneously.
Page 330: Processing Output
FIR Accelerator Processing Output The accelerator uses all four MACs simultaneously to calculate one output sample as shown in Figure 6-5 and the following procedure. Load chain pointer and control registers and enable accelerator Load coefficients for the iteration Prefill delay line Load next data Perform all MACS and calculate result...
Page 331: Internal Memory Storage
FFT/FIR/IIR Hardware Modules 1. The accelerator fetches four input data from the delay line and four corresponding coefficients from the coefficient memory and feeds them to the MAC units for multiply/accumulation. 2. The accelerator repeats the procedure with the next four input data and coefficients until all the TAPs complete.
Page 332 FIR Accelerator Single Rate Input Filtering The total size of the input buffer should at least be equal to N – 1 + W. If the input buffer that needs to be processed is: x[n],x[n+1],x[n+2] ..x[n+W-1] it should be stored in the memory as x[n-(N-1)], x[n-(N-2)] ..
Page 333: Operating Modes
FFT/FIR/IIR Hardware Modules x[n-(K-1)], x[n-(K-2)]..x[n-1], x[n], x[n+1]..x[n+W/L-1] and the IIFIR should point to x[n-(K-1)] Operating Modes The FIR core performs a sum-of-products operation to compute the con- volution sum. It supports single-rate, decimation, and interpolation functions. Single Rate Processing In a single-rate filter, the output result rate is equal to the input sample rate.
Page 334 FIR Accelerator In this example, the FIR controller implements two iterations of 256 taps and one iteration of 38 taps.  Multi-iteration mode is not supported in fixed-point format. Window Processing Sample based processing mode is selected by configuring window size to 1. In this mode, one sample from a particular channel is processed through all the biquads of that channel and the final output sample is calculated.
Page 335 FFT/FIR/IIR Hardware Modules The input buffer size for decimation filters is N – 1 + (W × M) where: • N is the number of taps • W is the window size • M is the decimation ratio The window size ( bits) in the register must be pro- WINDOW...
Page 336 FIR Accelerator The input buffer size issmallest integer greater than or equal to (N – 1 + W)/L for interpolation filters where: • N is the number of taps • W is the window size • L is the interpolation ratio To start the mode, programs configure the bits FIR_RATIO...
Page 337 FFT/FIR/IIR Hardware Modules 6. Processing moves to the next channel and repeats the procedure. If the soft filter length is more than the hard filter length, multiple iterations are done to process the window. Load I, M, B, L registers for coefficient and data I/O Load coefficients into coefficient memory...
Page 338 FIR Accelerator Floating-Point Data Format The FIR accelerator treats data and coefficients in 32-bit floating-point format as the default functional mode. Fixed-Point Data Format In fixed-point mode, the 32-bit input data/coefficient is treated as fixed-point. A 32-bit fixed-point MAC operation generates an 80-bit result.
Page 339 FFT/FIR/IIR Hardware Modules Chain Pointer DMA The DMA controller supports circular buffer chain pointer DMA. One transfer control block (TCB) needs to be configured for each channel. The TCB contains: • A control register value to configure the filter parameters for each channel •...
Page 340 FIR Accelerator  register is part of the FIR TCB. This allows program- FIRCTL2 ming individual FIR channels with different control attributes. Index Register Buffer Length Register Base Register Figure 6-7. Circular Buffer Addressing Interrupts The FIR accelerator has two interrupts (Table 6-3) that are programmable through the programmable interrupt priority control register...
Page 341 FFT/FIR/IIR Hardware Modules Interrupt Sources There are two types of DMA interrupt sources associated with the acceler- ator. The bit in the register controls these interrupts. FIR_CCINTR FIRCTL1 Window Complete Interrupt – This interrupt is generated at the end of each channel when all the output samples are calculated corresponding to a window and updated index values are written back.
Page 342 FIR Accelerator Bit 11 of the register selects coefficient memory if set (=1) and DBGADDR selects delay line memory in cleared (=0). In the debug mode, the read data register ( ) returns the con- DBGMEMRDDAT tents of the memory location pointed to by the address register. Data can be written into any memory location using register writes.
Page 343 FFT/FIR/IIR Hardware Modules an effect latency of two cycles. Wait for at least four cycles after PCLK CCLK selecting an accelerator before accessing any of its registers. FIR Throughput Accelerator input and output channels are used to connect to internal memory.
Page 344: Single Channel Processing
FIR Accelerator Additional Information It may be difficult to achieve the required performance by using sample based processing (Window size = 1). Increasing the window size provides more computation time and the ability to perform the real time process- ing. It is a common practice to use block based processing (Window size greater 1).
Page 345: Multichannel Processing
FFT/FIR/IIR Hardware Modules 2. Create the TCBs in internal memory. Each TCB corresponds to a particular channel. TCBs hold the register which allows programming the FIRCTL2 window size and tap size along with up or down sample enable, sample rate conversion enable, and the conversion ratio for decima- tion and interpolation filters.
Page 346 FIR Accelerator 1. Program the number of channels in the register using the FIRCTL1 bits (5–1). FIR_NCH 2. Configure the TCBs in internal memory with one channel’s TCB pointing to the next channel’s TCB. 3. Write the first TCB value into the register and enable the CPFIR accelerator.
Page 347 FFT/FIR/IIR Hardware Modules Core sets up control register and initiates RUN command Load TCB for current channel Process one window of current channel All channels done? Auto channel iterate? Wait for core intervention Figure 6-8. Wait for Core Intervention => Idle (if CAI bit = 0) ADSP-214xx SHARC Processor Hardware Reference 6-51 www.BDTIC.com/ADI...
Page 348: Debug Mode
FIR Accelerator Debug Mode The next sections show the steps required for reading and writing local memory in debug mode. Write to Local Memory 1. Enable the FIR module using the register. PMCTL1 2. Wait at least 4 cycles. CCLK 3.
Page 349: Single Step Mode
FFT/FIR/IIR Hardware Modules 6. Write start address to the register. Note if bit 11 is set, FIRDBGADDR coefficient memory is selected. 7. Wait at least 4 cycles. CCLK 8. Read data from the register. FIRDBGRDDATA Single Step Mode Single step mode can be used for debug purposes. An additional debug register is used in this mode.
Page 350 FIR Accelerator 2. Create six TCBs in internal memory with each channel’s chain pointer (CP) entry pointing to the next channel’s and the sixth channel’s CP entry pointing back to the first’s in a circular fashion. 3. Configure the register for the first four channels’ TCBs to FIRCTL2 256 TAPs and a window size of 128, and the next two channels for 1024 TAPs and a window size of 128, respectively.
Page 351: Iir Accelerator
FFT/FIR/IIR Hardware Modules IIR Accelerator The ADSP-214xx processors have an IIR filter accelerator implemented in hardware, that reduces the processing load on the core, freeing it up for other tasks. Features The accelerator supports a maximum of 24 channels. There is support for up to 12 cascaded bi-quads per channel.
Page 352: Clocking
IIR Accelerator DMA Status (IIRDMASTAT). Provides the status of accelerator opera- tion including chain pointer loading, coefficient DMA, processing progress, window complete and all channels complete. MAC Status (IIRMACSTAT). TProvides the status of the MAC operations. Debug Mode Control (IIRDEBUGCTL). Controls the debug mode operation of the accelerator.
Page 353 FFT/FIR/IIR Hardware Modules CORE PMD/DMD IOD0 IIR CONTROL IIR CONTROLLER CONTROLLER REGISTERS RESULT REGISTER BIQUAD BIQUAD BIQUAD BIQUAD BIQUAD BIQUAD STAGE 1 STAGE 1 BIQUAD BIQUAD STAGE 2 STAGE 2 BIQUAD BIQUAD DATA STAGE 3 BIQUAD STAGE 3 COEFF COMPUTE ACCESS STATE UNIT...
Page 354 IIR Accelerator Figure 6-10. Transposed Direct Form II Biquad The accelerator has the following logical sub blocks: • A data path unit with the following elements: • 32/40-bit coefficient memory for storing biquad coefficients • 32/40-bit data memory for the intermediate data •...
Page 355: Multiply And Accumulate (Mac) Unit
FFT/FIR/IIR Hardware Modules • A DMA bus interface for transferring data to and from the acceler- ator. This interface is also used to preload the coefficients and Dks at start up. • DMA configuration registers for the transfer of input data, output data and coefficients Multiply and Accumulate (MAC) Unit The MAC unit shown in...
Page 356: Data Memory
IIR Accelerator Data Memory The size of data memory is 576 x 40 bits and is used to hold the dk1 and dk2 intermediate data of all the biquads locally. The DMA controller fetches the sample data from internal memory and calculates the output as well as the dk1 and dk2 values for each biquad and stores them in data memory.
Page 357: Operating Modes
FFT/FIR/IIR Hardware Modules For N biquad stages, the order of coefficients should be as follows: b01, b11, –a11, b21, –a21, dk21, dk11, b02, b12, –a12, b22, –a22, dk22, dk12 ,..b0N, b1N, –a1N, b2N, –a2N, dk2N, dk1N. where bxN and axN are the coefficients ([b, a]) for the Nth biquad stage.
Page 358: Data Transfers
IIR Accelerator first 32-bit word provides the lower 32 bits and the 8 LSBs of the second 32-bit word provides rest of the upper 8 bits of the a complete 40-bit word. Figure 6-12 shows the 32-40 bit packing used by accelerator. ...
Page 359 FFT/FIR/IIR Hardware Modules • A control register value to configure the filter parameters for each channel • DMA parameter register values for the input data (delay line) • DMA parameter register values for coefficient load • DMA parameter register values for output data As shown in “IIR Accelerator TCB”...
Page 360: Interrupts
IIR Accelerator Accelerator input and output channels are used to connect to internal memory.  Note that the register is part of the IIR TCB. This allows IIRCTL2 to program individual IIR channels having different control attributes. Interrupts The IIR accelerator has two interrupts that are programmable through the registers ( Appendix B, Peripheral Interrupt Control).
Page 361 FFT/FIR/IIR Hardware Modules Channels Complete Interrupt – This interrupt is generated when all the channels are complete or when one iteration of time slots completes. MAC Status Interrupt – The status interrupt sources are derived from the register. For more information, see “IIR MAC Status Register FIRMACSTAT (IIRMACSTAT)”...
Page 362 IIR Accelerator The 40-bit wide debug mode write data register is organized as: • The register holds the lower 32 bits and IIRDBGWRDATA_L • The register holds the upper 8 bits IIRDBGWRDATA_H A read from the register followed by a read from the IIRDBGRDDATA_L register returns the content of the 40-bit memory loca- IIRDBGRDDATA_H...
Page 363 FFT/FIR/IIR Hardware Modules Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference. IIR Accelerator Effect Latency After the IIR registers are configured the effect latency is 1.5 cycles PCLK minimum and 2 cycles maximum. Writes to the register have PCLK PMCTL1...
Page 364 IIR Accelerator Programming Model The IIR supports up to 24 channels which are time division multiplexed (TDM). Each channel can have a maximum of 12 cascaded biquads. The window size for each channel is configurable using control registers. A window size of 1 corresponds to sample based operation and the maxi- mum window size is 64.
Page 365 FFT/FIR/IIR Hardware Modules Core sets up control register and initiates run Preload all the coefficients and initialize intermediate results Load TCB for current channel Move to next Process one window channel of current channel All channels done? Wait for core intervention Figure 6-14.
Page 366 IIR Accelerator 5. Set the bit in register for address auto IIR_ADRINC IIRDEBUGCTL increment. 6. Write start address to the register. If bit 11 is set, coef- IIRDBGADDR ficient memory is selected. 7. Wait at least 4 cycles. CCLK 8. Write data to the register.
Page 367 FFT/FIR/IIR Hardware Modules Single Step Mode Single step mode can be used for debug purposes. An additional debug register is used in this mode. 1. Enable stop DMA during breakpoint hit in the emulator settings. 2. Clear the bit and enable bits in IIR_HLD IIR_DBGMODE...
Page 368 IIR Accelerator 5. Configure the index, modifier, and length entries in the TCBs to point to the corresponding channel’s data buffer, coefficient buffer and output data buffer. The location of the first channel’s TCB is written to the chain pointer register in the accelerator. 6.
Page 369 7 PULSE WIDTH MODULATION Pulse width modulation (PWM) is a technique for controlling analog cir- cuits with a microprocessor’s digital outputs. PWM is employed in a wide variety of applications, ranging from measurement to communications to power control and conversion. The interface specifications are shown in Table 7-1.
Page 370 Features Table 7-1. PWM Specifications (Cont’d) Feature Availability DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation PCLK Features The following is a brief summary of the features of this interface. • Four independent PWM units •...
Page 371 Pulse Width Modulation • The emergency dead time insertion is implemented after the ‘ideal’ PWM output pair, including crossover, is generated. • The output control unit allows the redirection of the outputs of the two-phase timing unit for each channel to either the high-side or the low-side output.
Page 372 Pin Descriptions Pin Descriptions The PWM module has four groups of four PWM outputs each, for a total of 16 PWM outputs. These outputs are described in Table 7-2. Table 7-2. PWM Pin Descriptions Multiplexed Pin Direction Description Name PWM_AH3–0 PWM output of pair A produce high side drive signals.
Page 373 Pulse Width Modulation Table 7-3. PWM Connections (Cont’d) PWM Unit Pin Multiplexing PWM2 AMI_ADDR16 = AL2 AMI_ADDR17 = AH2 AMI_ADDR18 = BL2 AMI_ADDR19 = BH2 PWM3 AMI_ADDR20 = AL3 AMI_ADDR21 = AH3 AMI_ADDR22 = BL3 AMI_ADDR23 = BH3 SRU Programming The ADSP-2147x and 2148x can output the PWM units 3–1 over the DPI pins.
Page 374 Clocking • PWM status registers (PWMSTATx). Report the phase and mode status for each PWM group.  The traditional read-modify-write operation to enable/disable a peripheral is different for the PWMs. For more information, see “Global Control Register (PWMGCTL)” on page A-67. Clocking The fundamental timing clock of the PWM controllers is peripheral clock PCLK...
Page 375: Duty Cycles
Pulse Width Modulation clock increments in a PWM period (edge aligned mode) or in a half PCLK PWM period (center aligned mode) in half a PWM period. Therefore, the PWM switching period, T , can be written as: = 2 × PWMTM × t (edge aligned) PCLK = PWMTM ×...
Page 376 Functional Description two-phase timing unit over half the PWM period. The duty cycle register range is from: (–PWPERIOD ÷ 2 – PWMDT) to (+PWPERIOD ÷ 2 + PWMDT) which, by definition, is scaled such that a value of 0 represents a 50% PWM duty, cycle.
Page 377 Pulse Width Modulation PWMPERIOD PWMPERIOD PWMPERIOD count PWMCHA PWMCHA PWM_AH PWM_AL 2xPWMDT 2xPWMDT PWMPHASE PWMPERIOD PWMPERIOD PWM INTERRUPT LATCH BIT Figure 7-2. Center-Aligned Paired PWM in Single Update Mode, Low Polarity The resulting on-times (active low) of the PWM signals over the full PWM period (two half periods) produced by the PWM timing unit and illustrated in Figure 7-2...
Page 378 Functional Description The range of T × × PWMPERIOD – PCLK and the corresponding duty cycles are: -- - PWMCHA PWMDT – ------- - ------------------------------------------------------------------- - PWMPERIOD -- - PWMCHA PWMDT – ------ - ------------------------------------------------------------------- - PWMPERIOD The minimum permissible value of T and T is zero, which corre- sponds to a 0% duty cycle, and the maximum value is T...
Page 379 Pulse Width Modulation PWMPERIOD PWMPERIOD   × ----------------------------------------- ----------------------------------------- PWMCHA PWMCHA PWMDT PWMDT – –   PCLK PWMTM 1 PWMTM 1 PWMTM 2 PWMTM 2 count PWMCHA 1 PWMCHA 2 pwm_ah pwm_al 2xPWMDT 1 2xPWMDT 2 PWM PHASE BIT PWM INTERRUPT LATCH BIT PWMTM 1...
Page 380: Dead Time
Functional Description T AH PWMCHA 1 PWMCHA 2 PWMDT 1 PWMDT 2 – – ----------- - -- - ----------------------------------------------------------------------------------------------------------------------------------------- - PWMPERIOD PWMPERIOD since for the general case in double- update mode, the switching period is given by: × PWMPERIOD PWMPERIOD PCLK Again, the values of T and T...
Page 381: Output Control Unit
Pulse Width Modulation therefore be programmed in increments of 2 × PCLK (or 10 ns for a 200 MHz peripheral clock). The registers are 10-bit registers, and the PWMDTx maximum value they can contain is 0x3FF (= 1023) which corresponds to a maximum programmed dead time of: 9 –...
Page 382: Complementary Outputs
Functional Description required, provided the change is done a few cycles before the next period change. Complementary Outputs The PWM controller can be operatde in paired or non paired mode register). PWMCTLx In non paired mode (default) both outputs (high and low side) are driven independently.
Page 383: Emergency Dead Time For Over Modulation
Pulse Width Modulation In other words, both should be PWM_AL PWM_AH PWM_BL PWM_BH enabled and both should have same polarity for proper operation of cross-over mode. Emergency Dead Time for Over Modulation The PWM timing unit is capable of producing PWM signals with variable duty cycle values at the PWM output pins.
Page 384 Functional Description Inserting additional emergency dead time into one of the PWM signals of a given pair during these transitions is only needed if both PWM signals would otherwise be required to toggle within a dead time of each other. The additional emergency dead time delay is inserted into the PWM sig- nal that is toggling into the on state.
Page 385: Output Control Feature Precedence
Pulse Width Modulation PWMPERIOD 1 PWMTM 2 PWMPERIOD 1 PWMCHA 1 FULL ON PWM_AH 2xPWMDT PWM_AL FULL OFF PWM_AH 2xPWMDT PWM_AL EMERGENCY DEAD TIME INSERTED BY PWM CONTROLLER PWMPERIOD PWMPERIOD (a) TRANSITION FROM NORMAL MODULATION TO FULL-ON, AT HALF-CYCLE BOUNDARY IN DOUBLE UPDATE MODE, WHERE NO ADDITIONAL DEAD TIME IS NEEDED.
Page 386: Operation Modes
Operation Modes 4. Emergency Dead Time Insertion 5. Output Polarity Operation Modes The following sections provide information on the operating modes of the PWM module. Waveform Modes The PWM module can operate in both edge- and center-aligned modes. These modes are described in the following sections. Edge-Aligned Mode In edge-aligned mode, shown in Figure...
Page 387: Center-Aligned Mode
Pulse Width Modulation The PWM switching period time for edge aligned mode is: × PWMPERIOD. PCLK For more information see“Pulse Width Modulation Registers” on page A-67 PERIOD/2 DUTY PERIOD Figure 7-5. Edge Aligned PWM Wave with High Polarity Center-Aligned Mode Most of the following description applies to paired mode, but can also be applied to non-paired mode, the difference being that each of the four outputs from a PWM group is independent.
Page 388 Operation Modes Center-Aligned Non-Paired Mode. Generates independent signals on two outputs. In paired mode, the two’s-complement integer values in the 16-bit read/write duty cycle registers, , control the duty cycles of PWMAx PWMBx the four PWM output signals on the PWM_AL PWM_AH PWM_BL...
Page 389: Pwm Timer Edge Aligned Update
Pulse Width Modulation PWM TIME DECREMENTS FROM PWM TIME DECREMENTS FROM PWMPERIOD/2 TO -PWMPERIOD/2 -PWMPERIOD/2 TO PWMPERIOD/2 PWMPERIOD/2 PCLK -PWMPERIOD/2 PWMPHASE BIT PWM INTERRUPT LATCH (SINGLE UPDATE MODE) PWM INTERRUPT LATCH (DOUBLE UPDATE MODE) Figure 7-6. Operation of Internal PWM Timer (Center Aligned) PWM Timer Edge Aligned Update The internal operation of the PWM generation unit is controlled by the PWM timer which is clocked at the peripheral clock rate,...
Page 390: Single Update Mode
Operation Modes PWM TIME DECREMENTS FROM PWM TIME DECREMENTS FROM -PWMPERIOD/2 TO PWMPERIOD/2 PWMPERIOD/2 TO -PWMPERIOD/2 PWMPERIOD/2 PCLK -PWMPERIOD/2 PWM INTERRUPT LATCH Figure 7-7. Operation of Internal PWM Timer (Edge Aligned) Single Update Mode In single update mode, a single PWM interrupt is produced in each PWM period.
Page 391: Effective Accuracy
Pulse Width Modulation configuration registers, duty cycle registers and the register. As a PWMSEG result, it is possible to alter both the characteristics (switching frequency and dead time) as well as the output duty cycles at the mid-point of each PWM cycle.
Page 392: Synchronization Of Pwm Groups
Operation Modes in each half period (or 2 x for the full period). In double update PCLK mode, improved accuracy is possible since different values of the duty cycles registers are used to define the on times in both the first and second halves of the PWM period.
Page 393: Interrupts
Pulse Width Modulation The PWM sync enable feature allows programs to enable the bits to independently start the main counter without PWN_SYNC_ENx enabling the corresponding PWM module using the bits. To syn- PWM_ENx chronize different groups, enable the corresponding group’s bit at PWM_ENx the same time.
Page 394 Interrupts interrupts and is unmasked in the core. The registers PWMSEG PWMCHx are also written, depending on the system configuration and modes. Dur- ing the PWM interrupt driven control loop, only the duty values PWMCHx are typically updated. The register may also be updated for other PWMSEG system implementations requiring output crossover.
Page 395: Debug Features
Pulse Width Modulation Debug Features The module contains four debug status registers ( ), which can PWMDBG3–0 be used for debug aid. Each register is available per unit. The registers return current status information about the AH, AL, BH, BL output pins. Status Debug Register The module contains four debug status registers ( ), which can...
Page 396 Effect Latency 7-28 ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 397 8 MEDIA LOCAL BUS Media Local Bus (MediaLB®) is an on-PCB or inter-chip communication bus, which allows an application to access the MOST network data. Media Local Bus supports all the MOST network data transport methods including synchronous stream data, asynchronous packet data, control message data and isochronous data.
Page 398 Table 8-1. MLB Specifications (Cont’d) Feature Availability Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Interrupt Source Core/DMA Boot Capable Local Memory Clock Operation 50 MHz The MLB module in the ADSP-214xx serves as an interface between the...
Page 399 Media Local Bus Features The MLB device has the following features. • Support for both 3-pin and 5-pin MediaLB interfaces • Selectable MediaLB clock rate: 256Fs, 512Fs and 1024Fs • Support for control, streaming and packet data • Support for 31 channels, configured for any channel type (synchro- nous, asynchronous, control) and direction (transmit and receive) •...
Page 400 Register Overview Register Overview The following sections provide brief descriptions of the registers used by the MediaLB interface. For complete bit descriptions, see “Media Local Bus Registers” on page A-94. Device Configuration and Status Registers These registers are used to set up the basic features of the interface and to report status of the MLB network.
Page 401 Media Local Bus • Channel Interrupt Status Register (MLB_CICR). Reflects the channel interrupt status of the individual logical channels. These bits are set by hardware when a channel interrupt is generated. The channel interrupt bits are sticky and can only be reset by software. •...
Page 402 Functional Description to form a MLB logical channel, which is defined by a unique channel address. As shown in Figure 8-1, the MLB controller initiates communication by sending out a channel address on the line for each physical chan- MLBSIG nel.
Page 403 Media Local Bus fashion, receiving devices cannot return a busy status and should not drive RxStatus onto the line. MLBSIG For further information on the MediaLB Specification, please refer to the MediaLB specification document available on www.smsc-ais.com Operating Modes The following sections describe the operating modes of the MLB interface.
Page 404 Data Transfer Big-Endian and Little-Endian Mode The byte order in which data is transferred between local channel buffers and internal memory is determined by enabling either big-endian or lit- tle-endian mode. Both data transfer methods, DMA and I/O mode support big-endian and little-endian system memory data formats. This option is selected using the bit in the register.
Page 405 Media Local Bus the local channel buffer memory is 124 quadlets. At reset each channel has four quadlets each. BUFFER DEPTH BUFFER THRESHOLD TX DATA TX DATA OUTPUT INPUT FREE QUADLETS VALID DATA TRANSMIT SERVICE REQUEST GENERATED (NUMBER OF VALID DATA QUADLETS <= BUFFER THRESHOLD) BUFFER DEPTH BUFFER THRESHOLD RX DATA...
Page 406 Data Transfer • The number of free quadlets in the local channel buffer falls below the threshold for receive channels or: free quadlets <= (programmed using bits) MLB_LCBCRx • A receive channel detects a broken packet (ReceiverBreak, AsyncBreak, ControlBreak or ReceiverProtocolError). Configuring local channel buffer memory is accomplished using the register.
Page 407 Media Local Bus The lower 14 bits (00 0001 0000 0000) and the 2 reserved bits “00” are written in the register (write 0000 0100 0000 0000 = 0x0400 MLB_CNBCRx to bits 31–16 in the register for the start address or bits 15–0 MLB_CNBCRx for the end address).
Page 408 Data Transfer For ping-pong DMA mode, transmit and receive for all data types are handled in the following manner. • At the start of buffer processing, the beginning of the next buffer becomes the beginning of the current buffer, as the bits from register are loaded into the bit field of the...
Page 409 Media Local Bus Circular Buffer DMA Logical channels operate in circular buffer DMA mode when the channel mode select bits in the register are set to 01. This mode is MLB_CECRx available for synchronous channels only. In contrast to ping-pong buffer- ing, circular buffering uses a single, circular memory buffer to process channel data.
Page 410 Interrupts Interrupts The buffer start and buffer done interrupts (bit 19 and bit 18 respectively) can unmasked in the channel control registers ( ) to indicate the MLB_CECRx start and end of a DMA. The MLB interrupt is not selected as one of the 19 programmable interrupts by default.
Page 411 Media Local Bus Interrupt Source One interrupt is shared by the system status and channel status interrupts. Servicing Interrupts System status interrupts interrupts are generated on events that allow sys- tem software to monitor and control the status of the MediaLB Network. These interrupts can be unmasked by clearing the corresponding bit in register.
Page 412: I/O Interrupt Mode
Programming Model Loop-Back Test Mode Loop-back test mode is used for debug operations and is enabled by set- ting the bit in the register. This mode provides basic testing MLB_DCCR capabilities for the MediaLB pads, physical layer, link layer, channel pro- tocol and the local channel buffer by enabling a single receive channel and a single transmit channel.
Page 413: Dma Modes
Media Local Bus 7. Configure the logical channel using the register for I/O MLB_CECRx mode, transfer direction, channel type, channel address and inter- rupt generation. For a transmit, a transmit service request, ( bit 1 in the register) an interrupt is generated when the local chan- MLB_CSCRx nel buffer can accept data.
Page 414 Programming Model 4. Configure the MLB control register ( ) with the appropri- MLB_DCCR ate settings and enable the MediaLB device. 5. Configure the base address register ( MLB_SBCR MLB_ABCR ) based on the data type configured for the logical MLB_CBCR channel.
Page 415: Digital Application/Digital Peripheral Interfaces
9 DIGITAL APPLICATION/DIGITAL PERIPHERAL INTERFACES The digital application interface (DAI) and the digital peripheral interface (DPI) are comprised of a groups of peripherals and their respective signal routing units (SRU and SRU2). The inputs and outputs of the peripherals are not directly connected to external pins. Rather, the SRUs connect the peripherals to a set of pins and to each other, based on a set of configura- tion registers.
Page 416: Features
Features Table 9-1. Routing Unit Specifications (Cont’d) Feature Total Channels Miscellaneous I/O channels Peripheral Channels Local Memory Clock Operation PCLK PCLK Features The DAI/DPI incorporates a set of peripherals and a very flexible routing (connection) system permitting a large combination of signal flows. A set of DAI/DPI-specific registers make such design, connectivity, and func- tionality variations possible.
Page 417: Register Overview
Digital Application/Digital Peripheral Interfaces Register Overview The SRU for the DAI contains six register sets that are associated with the DAI groups. Clock Routing Registers (SRU_CLKx). Associated with Group A, routes clock signals. Serial Data Routing Registers (SRU_DATx). Associated with group B, routes data.
Page 418: Clocking
Clocking Pin Enable Signal Routing (SRU2_PBENx). Associated with group C used to specify whether each DPI pin is used as an output or an input by setting the source for the pin buffer enable. The DAI/DPI registers are unique in that they work as groups to control other peripheral functions.
Page 419 Digital Application/Digital Peripheral Interfaces The DAI/DPI pin buffers have three signals which are used for input/out- put to/from off-chip world and the 3rd for output enable. The miscellaneous buffers have an input and an output and are used for group interconnection. Note that Figure 9-1 is a simplified representation of a DAI system.
Page 420 Functional Description • GPIO flags (External Port) • DPI Interrupts (Miscellaneous)  Note that the precision clock generator (units C/D) can be assigned to access DAI and/or DPI pins. DAIHI SRU2 DAI/DPI DAILO CORE INTERRUPT INTERRUPT CONTROL PERIPHERAL INTERNAL DAI/DPI CHIP NODE PIN BUFFER...
Page 421: Dai/Dpi Signal Naming Conventions
Digital Application/Digital Peripheral Interfaces DAI/DPI Signal Naming Conventions Each peripheral associated with the DAI/DPI does not have any dedicated I/O pins for off-chip communication. Instead, the I/O pin is only accessi- ble in the chip internally and is known as an internal node. Every internal node of a DAI peripheral (input or output) is given a unique mnemonic.
Page 422: Pin Buffers As Signal Output
Functional Description DAI_PBxx_O External DAI DAI_PBxx_I Interface BUFFER pin buffer to SRU ENABLE PBENxx_I Figure 9-3. Pin Buffer Example The notation for pin input and output connections can be quite confusing at first because, in a typical system, a pin is simply a wire that connects to a device.
Page 423 Digital Application/Digital Peripheral Interfaces either an output or an input. Although the direction of a DAI pin is set simply by writing to a memory-mapped register, most often the pin’s direction is dictated by the designated use of that pin. For example, if the DAI pin were to be hard wired to only the input of another intercon- nected circuit, it would not make sense for the corresponding pin buffer to be configured as an input.
Page 424: Pin Buffers As Signal Input
Functional Description Pin Buffers as Signal Input When the DAI pin is to be used only as an input, connect the correspond- ing pin buffer enable to logic low as shown in Figure 9-5. This disables the buffer amplifier and allows an off-chip source to drive the value present on the DAI pin and at the pin buffer output.
Page 425: Pin Buffers As Open Drain
Digital Application/Digital Peripheral Interfaces Pin Buffers as Open Drain For peripherals like the TWI and SPI (multi processing), the bus protocol requires the pin drivers to work in open drain mode (Figure 9-6) for trans- mit and receive operation. The signal input of the assigned pin buffer is tied low.
Page 426: Unused Dai/Dpi Pins
Functional Description ustat2=dm(DAI_PIN_STAT); bit tst ustat2 DAI_PB10; if TF jump DAI_PB10_high; Unused DAI/DPI Pins If a DAI/DPI pin is not being used, its pin enable (for example ) and its input ( ) for its pin buffer should be con- DAI_PBENxx_I DAI_PBxx_I nected to low.
Page 427 Digital Application/Digital Peripheral Interfaces input sources collected from different groups. MISCxx_I 4. Some buffers allow signal inversion. The miscellaneous buffers acts as intermediate buffer connections between the peripheral’s source node and the pin buffer enable destination node. This allows for routing that are not possible among a single group. ...
Page 428: Dai/Dpi Peripherals
Functional Description Table 9-3. Miscellaneous DPI Buffer Routing Inputs Outputs Register Interrupt Miscellaneous Interrupt Signal DPI_PBENxx_I Trigger Inversion Routing SRU2_INPUT4 DPI_INT_05_I MISCB0_I DPI_INT_06_I MISCB1_I DPI_INT_07_I MISCB2_I SRU2_INPUT5 DPI_INT_08_I MISCB3_I DPI_INT_09_I MISCB4_I DPI_INT_10_I MISCB5_I DPI_INT_11_I MISCB6_I DPI_INT_12_I MISCB7_I DPI_INT_13_I MISCB8_I DAI/DPI Peripherals There are two categories of peripherals associated with the DAI and DPI.
Page 429 Digital Application/Digital Peripheral Interfaces SPORT0_CLK_I SPORT0_CLK_O SPORT0_CLK_PBEN_O SPORT0_FS_I SPORT0_FS_O SPORT0_FS_PBEN_O Interface to SRU SPORT0_DA_I SPORT0_DA_O SPORT0_DA_PBEN_O SPORT0_DB_I SPORT0_DB_O SPORT0_DB_PBEN_O Figure 9-8. SRU Connections for SPORT0 For each bidirectional line, the SPORT provides three separate signals. For example, a SPORT clock has three separate SRU connections (instead of one physical pin): •...
Page 430: Output Signals Without Pin Buffer Enable Control
Functional Description behave as documented in Chapter 10, Serial Ports. The SRU then becomes transparent to the peripheral. Figure 9-8 demonstrates SPORT0 properly routed to DAI pins 1 through 4; although it can be equally well routed to any of the 20 DAI pins. The pin buffer output enable signals ( ) supported by any x_PBEN_O...
Page 431 Digital Application/Digital Peripheral Interfaces The SRU for the DAI contains seven groups that are named sequentially A through F. Each group routes a unique set of signals with a specific pur- pose as shown below. • Group A routes clock signals •...
Page 432: Dai/Dpi Group Routing
Functional Description DAI/DPI Group Routing Each group has a unique encoding for its associated output signals and a set of configuration registers. For example, DAI group A is used to route clock signals. The memory-mapped registers, , contain bit fields SRU_CLKx corresponding to the clock inputs of various peripherals.
Page 433 Digital Application/Digital Peripheral Interfaces SPORT5_CLK_I SPORT4_CLK_I SPORT3_CLK_I DAI_PB01_O DAI_PB02_O DAI_PB03_O DAI_PB04_O DAI_PB05_O DAI_PB06_O DAI_PB07_O DAI_PB08_O DAI_PB09_O DAI_PB10_O DAI_PB12_O DAI_PB13_O DAI_PB14_O DAI_PB15_O DAI_PB16_O DAI_PB17_O DAI_PB18_O DAI_PB19_O DAI_PB20_O SPORT0_CLK_O SPORT1_CLK_O SPORT2_CLK_O SPORT3_CLK_O SPORT4_CLK_O SPORT5_CLK_O LOGIC LOW (0) LOGIC HIGH (1) SPORT5_CLK_I SPORT3_CLK_I SPORT4_CLK_I Select Field Select Field...
Page 434: Rules For Sru Connections
Functional Description Rules for SRU Connections There are two rules which apply to all routing: 1. Each input must connect to exactly one output 2. An output can feed any number of inputs As an example from Figure 9-9: • is routed to DAI_PB01_O SPORT5_CLK_I...
Page 435 Digital Application/Digital Peripheral Interfaces nop; SRU(LOW, DAI_PB14_I); // DAI pin 14 input level low nop; SRU(DAI_PB14_O, DAI_PB03_I); // connect DAI pin 14 to DAI pin 3 nop; SRU(DAI_PB14_O, DAI_INT_22_I); // connect DAI pin 14 to DAI interrupt 22 DAI_PB03_I PERIPHERAL PBEN03_I DAI_PB03 DAI_PB14_O...
Page 436 Functional Description Listing 9-2. SRU Connection Between DAI Pin Buffers and SPORTs SRU(SPORT0_CLK_PBEN_O, PBEN03_I); // DAI pin 3 as output nop; SRU(SPORT0_CLK_O, DAI_PB03_I); // connect to DAI pin 3 nop; SRU(SPORT0_CLK_O, SPORT1_CLK_I); // connect to SPORT1 nop; SRU(SPORT0_CLK_O, SPORT2_CLK_I); // connect to SPORT2 SPORT0_CLK_O DAI_PB03_I SPORT0...
Page 437 Digital Application/Digital Peripheral Interfaces Listing 9-3. SRU Connection SPORT/PCG to MISC/DAI Pin Buffers SRU(HIGH, PBEN03_I); // DAI pin 3 output nop; SRU(DAI_PB14_O, DAI_PB03_I); // connect pin 3 and 14 nop; SRU(PCG_CLKB_O, DAI_PB14_I); // connect PCG and pin 14 nop; SRU(SPORT2_FS_O, MISCA4_I); // connect SPORT to MISCA nop;...
Page 438 Functional Description DAI Routing Capabilities Table 9-1 provides an overview about the different routing capabilities for the DAI unit. The DAI groups allow routing of specific signals like clocks, data, frame syncs. Table 9-4. DAI Routing Capabilities DAI Group Input (xxxx_I) Output (xxxx_O) A–Clocks SPORT7–0...
Page 439 Digital Application/Digital Peripheral Interfaces Table 9-4. DAI Routing Capabilities DAI Group Input (xxxx_I) Output (xxxx_O) F–Pin Buffer DAI Pin Buffer Enable SPORT7–0 (clock, FS, data, TDV) Logic level high 20–1 MISCA5–0 Logic level low G–Shift Register SR_CLK_I SPORT7-0 (clk, FS) (ADSP-2147x SR_LAT_I SPORT7-0 AB (data)
Page 440: Pin Buffer Input
Functional Description Table 9-5. DPI Routing Capabilities (Cont’d) DPI Group Input (xxxx_I) Output (xxxx_O) C–Pin Buffer DPI Pin Buffer Enable Timer1–0 Logic level high Enable SPI (MOSI, MISO, DS, CLK) Logic level low SPIB (MOSI, MISO, DS, CLK) UART0 TX FLAG15–4 TWI (clock, data) MISCB8–0...
Page 441: Miscellaneous Signals
Digital Application/Digital Peripheral Interfaces signal present at the corresponding pin buffer input ( ) is driven PBxx_I off-chip as an output. When a pin buffer enable is cleared (= 0), the signal present at the corresponding pin buffer input is ignored. The pin enable control registers activate the drive buffer for each of the DAI/DPI pins.
Page 442: Dai Default Routing
DAI Default Routing signal paths enable a number of possible uses and connections for the DAI/DPI pins. A few examples include: • One pin’s input can be patched to another pin’s output, allowing board-level routing under software control. • A pin input can be patched to another pin’s enable, allowing an off-chip signal to gate an output from the processor.
Page 443 Digital Application/Digital Peripheral Interfaces IDP7-0_DAT_I DIR_I DIT_DAT_I SRC_3-0_DAT_IP_I SRC_3-0_TDM_OP_I SPORT0_DA_I SPORT1_DA_I SPORT1_DA_O SPORT0_DA_O Pin01 Pin05 PBEN_O PBEN_O SPORT0_DB_I SPORT1_DB_I SPORT1_DB_O SPORT0_DB_O Pin02 Pin06 PBEN_O PBEN_O SPORT0_CLK_I SPORT1_CLK_I SPORT0_CLK_O SPORT1_CLK_O Pin03 Pin07 PBEN_O PBEN_O SPORT0_FS_I SPORT1_FS_I SPORT0_FS_O SPORT1_FS_O Pin04 Pin08 PBEN_O PBEN_O Figure 9-13.
Page 444 DAI Default Routing SPORT2_DA_I SPORT4_DA_I SPORT2_DA_O SPORT4_DA_O Pin09 Pin15 PBEN_O PBEN_O SPORT2_DB_I SPORT4_DB_I SPORT2_DB_O SPORT4_DB_O Pin10 Pin16 PBEN_O PBEN_O SPORT2_CLK_I SPORT4_CLK_I SPORT2_CLK_O SPORT4_CLK_O PBEN_O PBEN_O SPORT2_FS_I SPORT4_FS_I SPORT2_FS_O SPORT4_FS_O PBEN_O PBEN_O SPORT3_CLK_I SPORT5_CLK_I SPORT5_CLK_O SPORT3_CLK_O Pin13 Pin19 PBEN_O PBEN_O SPORT3_FS_I SPORT5_FS_I SPORT3_FS_O SPORT5_FS_O...
Page 445: Dpi Default Routing
Digital Application/Digital Peripheral Interfaces DPI Default Routing When the processor comes out of reset, some default routing is established (Figure 9-15). This scheme allows systems to use the SPI as either master or slave (without changing the routing scheme). Programs only need to use the SPI control register settings to configure master or slave operation.
Page 446: Interrupts
Interrupts  All DPI inputs which are not routed by default are tied to signal low. The default routing is used for SPI master/slave booting. Interrupts The DAI contains a dedicated interrupt controller that signals the core when DAI peripheral events occur. System Versus Exception Interrupts Generally, interrupts are classified as system or exception.
Page 447: Functional Description
Digital Application/Digital Peripheral Interfaces broad categories, programs can indicate which interrupts are high and which are classified as low. Functional Description There are several registers in the DAI interrupt controller that can be con- figured to control how the DAI interrupts are reported to and serviced by the core’s interrupt controller.
Page 448: Dai Interrupt Priorities
Interrupts DAI Interrupt Priorities As described above, the DAI interrupt controller registers provide 32 inde- pendently-configurable interrupts labeled DAI_INT31–0 Just as the core has its own interrupt latch registers ( IRPTL LIRPTL the DAI has its own latch registers ( ).
Page 449: Dai Miscellaneous Interrupts
Digital Application/Digital Peripheral Interfaces DAI Miscellaneous Interrupts As described above, the DAI interrupt controller registers provide 10 inde- pendently-configurable interrupts labeled as . Any trigger DAI_31-22_INT on the routed DAI inputs can cause an interrupt latch DAI_INT_31-22_I event in register if unmasked. DAI_IMASK ...
Page 450: Dai/Dpi Interrupt Mask Events
Interrupts  There are two signal naming conventions: the DPI interrupt con- troller bits are named and its corresponding SRU DPI_13-5_INT signals are named MISCB8-0_I Signals from the SRU2 group C can be used to generate interrupts. For example, when (bit 13) of is set to one, any signals DPI_13_INT...
Page 451 Digital Application/Digital Peripheral Interfaces indicates the signal type. When the protocol changes, output (signal) type is noted. For audio applications, the ADSP-214xx processors need information about interrupt sources that correspond to waveforms (not event signals). As a result, the falling edge of the waveform may be used as an interrupt source as well.
Page 452: Dai Interrupt Acknowledge
Interrupts Enabling responses to changes in conditions of signals (including changes in DMA state, introduction of error conditions, and so on) can only be done using the register. DAI_IMASK_RE DAI Interrupt Acknowledge Any asynchronous or synchronous interrupt causes a latency, since it forces the core to stop processing an instruction in process, then vector to the interrupt service routine (ISR), (which is basically an interrupt vector table (IVT) lookup), then proceed to implement the instruction refer-...
Page 453: Dpi Interrupt Acknowledge
Digital Application/Digital Peripheral Interfaces latched in one of the registers, all of them must be ser- DAI_IMASK_x viced before executing an RTI instruction. For more information, see “Interrupt Controller Registers” on page A-149. DPI Interrupt Acknowledge Any asynchronous or synchronous interrupt causes a latency, since it forces the core to stop processing an instruction in process, then vector to the interrupt service routine (ISR), (which is basically an interrupt vector table (IVT) lookup), then proceed to implement the instruction refer-...
Page 454: Debug Features
Debug Features registers provide a way to specify which interrupts to notice and handle, and which interrupts to ignore. These dual registers function like IMASK does, but with a higher degree of granularity.  The DAI/DPI interrupt controller has the same interrupt latency like the core interrupt controller which takes 6 cycle latency to respond to asynchronous interrupts.
Page 455 Digital Application/Digital Peripheral Interfaces The SRU can be used for this purpose. Table 9-9 describes the different possible routings based on the peripheral.  The peripheral’s loop back mode for debug is independent from both of the signal routing units. Table 9-9.
Page 456: Effect Latency
Effect Latency Effect Latency The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific). Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference. Signal Routing Unit Effect Latency After the DAI/DPI registers are configured the effect latency is 2 PCLK...
Page 457: Dai Example System
SRU(DAI_PB14_O,IDP3_FS_I); /* Connect pin buffer enable 19 to logic low */ SRU(LOW,PBEN19_I); Additional example code is available on the Analog Devices Web site.  There is a macro that has been created to connect peripherals used in a DAI configuration. This code can be used in both assembly and C code.
Page 458 Programming Model CLOCK SOURCE FROM S/PDIF DVD PLAYER FRAME SYNC SHARC STREAM S/PDIF S/PDIF serial CHANNEL0 PIN_1 SERIAL DATA CORE RECEIVER protocal containing multichannel audio sampled at 48 KHz S DATA INTO SHARC CORE TRANSLATE PROTOCOL and compressed in AC3 CONNECT TO S/PDIF RX AC3 (Dolby Digital) On-chip DPLL used to...
Page 459: 10 Serial Ports
10 SERIAL PORTS The processors have eight independent, synchronous serial ports (SPORTs) that provide an I/O interface to a wide variety of peripheral devices. They are called SPORT0, SPORT1, SPORT2, SPORT3, SPORT4, SPORT5, SPORT6, and SPORT7. Each SPORT has its own set of control registers and data buffers.
Page 460: Features
Features Table 10-1. Serial Port Specifications (Cont’d) Feature SPORT7–0[AB] Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access DMA Channels 2 per SPORT DMA Chaining Boot Capable Local Memory Clock Operation /4 (f /8, if SPORT is slave trans- PCLK PCLK mitter or master receiver)
Page 461 Serial Ports unidirectional streams into or out of the same serial port. This bidirectional functionality provides greater flexibility for serial communications. Further, two SPORTs can be combined to enable full-duplex, dual-stream communications. Serial ports can operate at a maximum of one-fourth the peripheral clock rate of the processor.
Page 462: Pin Descriptions
Pin Descriptions Pin Descriptions Table 10-2 describes pin function. Table 10-2. SPORT Pin Descriptions Internal Node Direction Description SPORT7–0_DA_I/O Data receive or transmit channel A. Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to receive serial data.
Page 463: Sru Programming
Serial Ports SRU Programming Any of the serial port’s signals can be mapped to digital applications inter- face ( ) pins through the signal routing unit (SRU) as shown in DAI_Px Table 10-3. For more information, see Chapter 9, Digital Applica- tion/Digital Peripheral Interfaces.
Page 464: Sru Sport Receive Master
SRU Programming Table 10-3. SPORT DAI/SRU Signal Connections (Cont’d) Internal Node DAI Connection SRU Register SPORT7–0_CLK_PBEN_O Group F SPORT7–0_FS_PBEN_O SPORT7–0_DA_PBEN_O SPORT7–0_DB_PBEN_O SPORT7–0_TDV_PBEN_O SRU SPORT Receive Master If the SPORT is operating as receive master, it must feed its master output clock back to its input clock.
Page 465: Register Overview
Serial Ports By redirecting the signals as shown in Figure 10-1 where the clock and frame sync outputs are routed directly back to their respective inputs, the signal sensitivity issue can be avoided. SPORT0_CLK_I DAI_PB01_O DAI_PB01_O EXTERNAL SPORT0_CLK_O PACKAGE ENABLE DAI_PB01_I CONNECTION SPORT0_CLK_PBEN_O...
Page 466: Clocking
Clocking operation mode, refer to Table 10-7 on page 10-24 “Operation Modes” on page 10-21. Serial Port Error Registers (SPERRxx). Two error registers ( SPER- ) are used to observe and control error handling during RCTLx SPERRSTAT transfers. Detected errors can be frame sync violation or buffer over/underflow conditions.
Page 467: Master Frame Sync
Serial Ports frame sync ( ) is considered a receive frame sync if the data SPORTx_FS signals are configured as receivers. Likewise, the frame sync SPORTx_FS considered a transmit frame sync if the data signals are configured as transmitters. The divisor is a 15-bit value, (bit 0 in divisor register is reserved) allowing a wide range of serial clock rates.
Page 468: Slave Mode
Functional Description The frame sync is continuously active when = 0. The value of FSDIV FSDIV should not be less than the serial word length minus one (the value of the field in the serial port control register), as this may cause an external SLEN device to abort the current operation or cause other unpredictable results.
Page 469: Architecture
Serial Ports • “Data Types and Companding” on page 10-12 • “Frame Sync” on page 10-16 Architecture A serial port receives serial data on one of its bidirectional serial data sig- nals configured as inputs, or transmits serial data on the bidirectional serial data signals configured as outputs.
Page 470: Data Types And Companding
Functional Description Figure 10-2 shows a block diagram of a serial port. Setting the SPTRAN enables the data buffer path, which, once activated, responds by shifting data in response to a frame sync at the rate of . An application SPORTx_CLK program must use the correct serial port data buffers, according to the value of...
Page 471 Serial Ports IOD0 BUS PM/DM DATA BUS TXSPxB RXSPxB RXSPxA TRANSMIT DATA RECEIVE DATA TXSPxA RECEIVE DATA BUFFER BUFFER TRANSMIT DATA BUFFER BUFFER HARDWARE HARDWARE COMPANDING COMPANDING (EXPANSION) (COMPRESSION) SPORTS 1, 3, 5, 7 ONLY SPORTS 0, 2, 4, 6 ONLY TRANSMIT RECEIVE RECEIVE SHIFT...
Page 472: Transmit Path
Functional Description companding algorithms, A-law and μ-law, performed according to the CCITT G.711 specification. The type of companding can be selected independently for each SPORT. Companding is selected by the DTYPE field of the control register. SPCTLx  Companding is supported on the A channel only. SPORT0, 2, 4 and 6 primary channels are capable of compression, while SPORTs 1, 3, 5 and 7 primary channels are capable of expansion.
Page 473: Receive Path
Serial Ports  signal is always driven if the serial SPORTx_DA SPORTx_DB port is enabled as transmitter ( = 1 in the SPEN_A SPEN_B SPCTLx control register), unless it is in multichannel mode and an inactive time slot occurs. When the SPORT is configured as a transmitter ( = 1), the SPTRAN TXSPxA...
Page 474: Frame Sync
Functional Description When the SPORT is configured as a receiver ( = 0), the receive buf- SPTRAN fers are activated. The receive buffers act like a three-location FIFO because they have two data registers plus an input shift register. Frame Sync The following sections provide information on frame syncs which applies to the SPORTs in all operating modes.
Page 475 Serial Ports As shown in Figure 10-3 the SPORT uses two control signals to sample data. 1. Serial clock ( ) applies the bit clock for each serial data. SCLK 2. Frame sync ( ) divides the incoming data stream into frames. Frames define the required data length (after the serial to parallel conver- sion) necessary to store the data in memory for further processing as shown in...
Page 476: Serial Word Length
Functional Description Serial Word Length The serial word length is not unique and is based on the operation mode. Moreover the companding feature limits the word length settings. Words smaller than 32 bits are right-justified in the receive and transmit buffers, residing in the least significant (LSB) bit positions (Table 10-4).
Page 477: External Frame Sync Sampling
Serial Ports Note that for I S and left-justified mode, the bit allows programs to MSTR select only the clock and frame sync to be simultaneously configured as master or slave. External Frame Sync Sampling A variety of framing options are available on the SPORTs as shown in Table 10-5.
Page 478: Logic Level Frame Syncs
Functional Description Logic Level Frame Syncs Frame sync signals may be active high or active low (for example, inverted). The bit in the registers selects the logic level of LMFS SPCTLx the frame sync signals as active low (inverted) if set (=1) or active high if cleared (=0).
Page 479: Operation Modes
Serial Ports Operation Modes SPORTs operate in five modes: • Standard serial mode, described in “Standard Serial Mode” on page 10-25 • Left-justified mode, described in “Left-Justified Mode” on page 10-28 • I S mode, described in “I2S Mode” on page 10-30 •...
Page 480 Operation Modes Table 10-6. SPCTLx Control Bit Comparison Standard Serial Packed Mode Multichannel Mode S and Mode Left-justified Mode Control SPEN_A Reserved 1–2 DTYPE Reserved DTYPE LSBF Reserved LSBF 4–8 SLEN PACK ICLK MSTR ICLK OPMODE CKRE Reserved CKRE Reserved Reserved IMFS DIFS...
Page 481: Mode Selection
Serial Ports Table 10-6. SPCTLx Control Bit Comparison (Cont’d) Standard Serial Packed Mode Multichannel Mode S and Mode Left-justified Mode Status DERR_B 27–28 DXS_B DERR_A 30–31 DXS_A Mode Selection The serial port operating mode can be selected via the and the SPCTLx registers.
Page 482: Channel Order First
Operation Modes control ( ) registers that must be set in order to configure each spe- SPCTLx cific SPORT operation mode. The shaded columns indicate that the bits come from different control registers. Table 10-7. SPORT Operation Modes SPCTLx Bits SPMCTLx Bits OPMODE OPMODE...
Page 483: Standard Serial Mode
Serial Ports Table 10-8. Channel Order First OPMODE L_FIRST = 0 L_FIRST = 1 Left-Justified Data first after rising edge Data first after falling edge Packed Data first after rising edge Data first after falling edge Data first after falling edge Data first after rising edge Standard Serial Mode The standard serial mode lets programs configure serial ports for use by a...
Page 484: Clocking Options
Operation Modes Clocking Options In standard serial mode, the serial ports can either accept an external serial clock or generate it internally. The bit in the register deter- ICLK SPCTL mines the selection of these options. For internally-generated serial clocks, bits in the register configure the serial clock rate.
Page 485: Early Versus Late Frame Syncs
Serial Ports Figure 10-4 illustrates framed serial transfers. SPORTX_CLK FRAMED DATA UNFRAMED DATA Figure 10-4. Framed Versus Unframed Data Early Versus Late Frame Syncs Frame sync signals can be early or late. Frame sync signals can occur dur- ing the first bit of each data word or during the serial clock cycle immediately preceding the first bit.
Page 486: Left-Justified Mode
Operation Modes When is set (=1), late frame syncs are configured. In this mode, the LAFS first bit of the transmit data word is available (and the first bit of the receive data word is latched) in the same serial clock cycle that the frame sync is asserted.
Page 487: Master Serial Clock And Frame Sync Rates
Serial Ports Master Serial Clock and Frame Sync Rates The serial clock rate ( value) for internal clocks can be set using a CLKDIV bit field in the register and the frame sync rate for internal frame sync DIVx can be set using the bit field in the register based on the FSDIV...
Page 488: I 2 S Mode
Operation Modes SPORTx_CLK SPORTx_FS/WS LEFT-JUSTIFIED SAMPLE LSB n-1 MSB n LSB n MSB n+1 PAIR MODE SPORTx_DA/DB DATA SAMPLE n-1 SAMPLE n SAMPLE n+1 LEFT CHANNEL Figure 10-6. Word Select Timing in Left-Justified Mode S Mode The following sections provide information on using I S mode.
Page 489: Multichannel Mode
Serial Ports • Word length ( , 8–32 bits) SLEN • Channel Order ( L_FIRST • Word Packing ( PACK  S mode is simply a subset of the left-justified mode. Note that in S mode, the data is delayed by one cycle and the operation SCLK transfer starts on the left channel first (...
Page 490: Clocking Options
Operation Modes The serial port can automatically select some words for particular channels while ignoring others. Up to 128 channels are available for transmitting or receiving or both. Each SPORT can receive or transmit data selectively from any of the 128 channels. Data companding and DMA transfers can also be used in multichannel mode on channel A.
Page 491 Serial Ports  Multichannel mode operates completely independently and each uses its own signal programmed using the SRU. The SCLK signal synchronizes the channels and restarts each multichannel sequence. The signal initiates the start of the channel 0 SPORTx_FS data word. The period in multichannel is defined as: period = ×...
Page 492 Operation Modes Figure 10-8 shows an example of timing for a multichannel transfer with SPORT pairing using SPORT0 and 1. The transfer has the following characteristics. • SPORT1–0 have the same and frame sync as input. SCLK • Multichannel is configured as 8 channels. •...
Page 493 Serial Ports three-stated when the time slot is not active, the signal spec- SPORTx_TDV_0 ifies if the SPORT data is being driven by the processor. Unlike previous SHARC processors, the assertion of the SPORTx_TDV_0 independent for the transmit buffer status (valid data or not). So writing to the buffer does not affect the output timing.
Page 494 Operation Modes field is a read-only status indicator. The bits increment modulo CHNL(6:0) as each channel is serviced. NCH(6:0) Active Channel Selection Registers Specific channels can be individually enabled or disabled to select the words that are received and transmitted during multichannel communica- tions.
Page 495 Serial Ports Companding Limitations (ADSP-2146x) In multichannel mode there is an option to enable companding for any active channel. If the first active channel is NOT the channel 0 and com- panding is enabled for the first active channel (channel 2), then from the second frame onward companding for the first active channel (channel 2) does not occur.
Page 496 Operation Modes for every frame, and therefore emulates I S mode. So it is a hybrid between multichannel and I S mode. L/RCLK BCLK SLOT 1 SLOT 2 SLOT 3 BLANK SLOT SLOT 4 SLOT 5 SLOT 6 BLANK SLOT DATA LEFT 0 LEFT 1...
Page 497 Serial Ports Timing Control Bits Several bits in the register enable and configure packed mode. SPCTLx • Internal Clock ( ICLK • Internal Frame Sync ( • Sampling Edges Frame Sync/Data ( CKRE • Selecting Channel Order ( L_FIRST • Word Length ( , 8–32 bits) SLEN •...
Page 498 Data Transfers transfers to/from the serial port buffers ( , and TXSPxA TXSPxB RXSPxA RXSPxB Data Buffers When programming the serial port channel (A or B) as a transmitter, only the corresponding buffers become active while the TXSPxA TXSPxB receive buffers remain inactive.
Page 499 Serial Ports Receive Buffers (RXSPxA/B) The receive buffers ( ) are the 32-bit receive data buf- RXSP7–0A RXSP7–0B fers SPORT7–0 respectively. These 32-bit buffers become active when the SPORT is configured to receive data on the A and B channels. When a SPORT is configured as a receiver, the registers are RXSPxA...
Page 500 Data Transfers  If the SPORTs are configured as transmitters, programs should not write to the inactive buffers. If the core keeps TXSPxA TXSPxB writing to the inactive buffer, the transmit buffer status becomes full. This causes the core to hang indefinitely since data is never transmitted to the output shift register.
Page 501 Serial Ports  When 16-bit received data is packed into 32-bit words and stored in normal word space in processor internal memory, the 16-bit words can be read or written with short word space addresses Core Transfers The following sections provide information on core driven data transfers. Single Word Transfers Individual data words may also be transmitted and received by the serial ports, with interrupts occurring as each 32-bit word is transmitted or...
Page 502 Data Transfers Frame Sync Generation The frame syncs are generated if the transmit or receive buffers are updated according to the bit setting (=0). If there is no buffer update DIFS by the core, the frame sync out is not driven off-chip and data output is zero.
Page 503 Serial Ports Each transmitter and receiver has its own DMA registers. The same DMA channel drives the left and right I S channels for the transmitter or the receiver. The software application must stop multiplexing the left and right channel data received by the receive buffer, because the left and right data are interleaved in the DMA buffers.
Page 504 Data Transfers and then transferring it to external memory using DMA. The ADSP-214xx processors allow direct DMA transfers between SPORTs and external memory which removes this overhead, freeing up the core and internal memory for other peripherals. The SPORT DMA and chain pointer registers have been expanded to hold the external memory address.
Page 505 Serial Ports DMA Chaining Each channel also has a DMA chaining enable bit ( SCHEN_A SCHEN_B in its control register. SPCTLx Each SPORT DMA channel also has a chain pointer register ( CPSPxy register functions are used in chained DMA operations. CPSPxy In chained DMA operations, the processor’s DMA controller automati- cally sets up another DMA transfer when the contents of the current...
Page 506 Data Transfers Moreover, transmitting or receiving words smaller than five bits may cause incorrect operation when all the DMA channels are enabled with no DMA chaining. DMA Chain Insertion Mode It is possible to insert a single SPORT DMA operation or another DMA chain within an active SPORT DMA chain.
Page 507 Serial Ports • In standard mode the bit (in the register) defines FS_BOTH SPCTLx the conditions of whether both channels are logically ANDed or ORed. • For all other operating modes, channels A and B are logically ANDed. If both channels are enabled, both buffers need to be updated by the DMA controller to drive data and frame sync off-chip.
Page 508 Interrupts Internal Transfer Completion Each serial port has an interrupt associated with it. For each SPORT, both the A and B channel transmit and receive data buffers share the same interrupt vector. The interrupts can be used to indicate the completion of the transfer of a block of serial data when the serial ports are configured for DMA.
Page 509 Serial Ports The SPORT generates an interrupt when the transmit buffer has a vacancy or the receive buffer has data. To determine the source of an interrupt, applications must check the transmit or receive data buffer sta- tus bits ( ) in registers and for DMA the corresponding DXS_A...
Page 510 Interrupts ERRONEOUS SLEN COUNTER NOT ZERO EARLY FS => SPERRI INTERRUPT DRIVE SCLK DRIVE SDRIVE DATA SAMPLED SLEN COUNTER SAMPLED DATA Figure 10-10. Frame Sync Error Detection When a serial port is receiving or transmitting, its bit count is set to a word length (for example 32 bits).
Page 511 Serial Ports • When the frame sync pulse > period. SCLK • In late frame sync mode if the frame sync pulse is not active during the whole transmission/reception a frame sync error is generated. Error Status Each SPORT can generate an interrupt if a , or DERR_A DERR_B...
Page 512 Effect Latency SPORT Loopback When the SPORT loopback bit, (bit 12), is set in the register, SPMCTLx the serial port is configured in an internal loopback connection as follows: SPORT0/SPORT1 work as a pair, SPORT2/SPORT3 work as a pair, SPORT4/SPORT5 work as a pair and SPORT6/SPORT7 work as a pair. ...
Page 513 Serial Ports Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference. SPORT Effect Latency After a write to a SPORT control register, control and mode bit changes take effect in the second serial clock cycle ( SCLK The SPORT is ready to start transmitting or receiving three serial clock cycles after they are enabled in the...
Page 514 Programming Model 3. Configure all DMA parameter registers (index, modify and count). 4. Configure the SPORT operation mode and enable DMA operation SPCTLx Setting Up and Starting Chained DMA To set up and initiate a chain of DMA operations, use the following procedure.
Page 515 Serial Ports 3. Write the start address of the first TCB of the new chain into the chain pointer register. 4. Resume chained DMA mode by setting = 1 and = 1. SDENx SCHENx Setting Up and Starting Multichannel Mode Use the and channel selection registers ( ) to configure the...
Page 516 Programming Model become non-empty by polling the bits. For core mode DXS0_A operation, initialize the transmit buffer with the first data word to be transmitted. 7. Configure and enable multichannel in the multichannel control registers ( SPMCTLx SPMCTLy Multichannel Mode Backward Compatibility In previous SHARC models, the serial port pair used the same control reg- ister ( ) to program multichannel mode.
Page 517 Serial Ports Programming Packed Mode Since packed mode is implemented on top of multichannel mode, pro- gramming this mode is the same as programming multichannel mode. Use the serial port control ( ) and channel selection registers ( SPCTLx SPMCTLx to configure the serial ports to run in packed mode as follows.
Page 518 Programming Model  In the ADSP-214xx processors the bit in the register FSED SPCTLN allows SPORT initialization regardless of the state of the external frame sync. The SPORT starts the transfer on the next valid edge. Companding As a Function Since the values in the transmit and receive buffers are actually com- panded in place, the companding hardware can be used without transmitting (or receiving) any data, for example during testing or debug-...
Page 519 Serial Ports With companding enabled, interfacing the serial port to a codec requires little additional programming effort. If companding is not selected, two formats are available for received data words of fewer than 32 bits—one that fills unused MSBs with zeros, and another that sign-extends the MSB into the unused bits.
Page 520 Programming Model 10-62 ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 521 11 INPUT DATA PORT The Input Data Port (IDP) compromises two units: the serial input port (SIP) and the parallel data acquisition port (PDAP). Located inside the DAI of the SHARC processor it provides an efficient way of transferring data from DAI pin buffers, the external port, the asynchronous sample rate converters (ASRC) and the S/PDIF transceiver to the internal mem- ory of SHARC.
Page 522 Features Table 11-1. IDP Port Specifications (Cont’d) Feature PDAP Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation PCLK PCLK Features The following list describes the IDP features. • The IDP provides a mechanism for a large number of asynchro- nous channels (up to eight).
Page 523 Input Data Port Pin Descriptions Table 11-2 provides descriptions of the IDP pins used for the serial inter- face port. Table 11-2. SIP Pin Descriptions Internal Node Description IDP7–0_CLK_I Serial Input Port Receive Clock Input. This signal must be gener- ated externally and comply to the supported input formats.
Page 524 Pin Descriptions Table 11-3. PDAP Pin Descriptions (Cont’d) Internal Nodes Type Description PDAP_STRB_O Parallel Data Acquisition Port Clock input. The PDAP packing unit asserts the output strobe whenever there is 32-bit data available for transfer to the IDP FIFO. The width of this pulse is equal to 2 x PCLK cycles.
Page 525 Input Data Port SRU Programming The SRU (signal routing unit) needs to be programmed in order to con- nect the IDP to the output pins as shown in Table 11-5. Table 11-5. IDP DAI/SRU Signal Connections Internal Node DAI Group SRU Register Inputs IDP7–0_CLK_I...
Page 526 Clocking IDP Control Registers (IDP_CTLx). The ADSP-2136x and ADSP-2137x SHARC processors have two IDP control registers. The registers are used to control the SIP operations. IDP_CTL1-0 PDAP Control Register (IDP_PP_CTL). The register (shown in Figure 11-1) is used to control all PDAP operations. IDP Status Register (IDP_STAT).
Page 527 Input Data Port The parallel data is acquired through the parallel data acquisition port (PDAP) which provides a means of moving high bandwidth data to the core’s memory space. The data may be sent to memory as one 32-bit word per input clock cycle or packed together (for up to four clock cycles worth of data).
Page 528 Operating Modes Operating Modes The following sections provide information on the various operation modes used by the PDAP module. The IDP has access to the IDP FIFO in the three modes listed below. The bit settings that configure these modes are shown in Table 11-7.
Page 529 Input Data Port PDAP Port Selection The input to channel 0 of the IDP is multiplexed, and may be used either in the serial mode or in a direct parallel input mode. Setting the PDAP_EN bit high disables the connection of SIP0 to channel 0 of the FIFO. The data inputs can come either from the DAI pins or the external port ADDR pins.
Page 530 Operating Modes Figure 11-3 on page 11-11 through Figure 11-5 on page 11-13 show dif- ferent packing modes including valid data hold inputs. As shown in the figures, are driven by the inac- PDAP_DATA PDAP_HOLD tive edges of the clock (falling edge in the above figures) and these signals are sampled by the active edge of the clock (rising edge in the figures).
Page 531 Input Data Port This mode sends one 32-bit word to FIFO for each input clock cycle—the DMA transfer rate matches the PDAP input clock rate. PDAP_CLK_I PDAP_HOLD_I PDAP DATA PDAP_STROBE_O PDAP_CLK_I PDAP_HOLD_I PDAP DATA PDAP_STROBE_O Figure 11-3. PDAP Hold Input (No Packing) Packing by 2 Packing by 2 moves data in two cycles.
Page 532 Operating Modes PDAP_CLK_I PDAP_HOLD_I PDAP DATA PDAP_STROBE_O PDAP_CLK_I PDAP_HOLD_I PDAP DATA PDAP_STROBE_O Figure 11-4. PDAP Hold Input (Packing by 2) Packing by 3 Packing by 3 packs three acquired samples together. Since the resulting 32-bit word is not divisible by three, up to ten bits are acquired on the first clock edge and up to eleven bits are acquired on each of the second and third clock edges: •...
Page 533 Input Data Port Packing by 4 Packing by 4 moves data in four cycles. Each input word can be up to eight bits wide. • On clock edge 1, bits 19–12 are moved to bits 7–0 • On clock edge 2, bits 19–12 are moved to bits 15–8 •...
Page 534 Data Transfer Data Transfer The data from each of the eight IDP channels is inserted into an eight reg- ister deep FIFO, which can only be transferred to the core’s memory space sequentially. Data is moved into the FIFO as soon as it is fully received. One of two methods can be used to move data from the IDP FIFO to internal memory: •...
Page 535 Input Data Port Table 11-8. IDP_FIFO Register Bit Descriptions Name Description 2–0 CHAN_ENC IDP Channel Encoding. These bits indicate the serial input port channel number that provided this serial input data. Note: This information is not valid when data comes from the PDAP. LR_STAT Left/Right Channel Status.
Page 536 Data Transfer The three LSBs of FIFO data are the encoded channel number. These are transferred “as is” for this mode. These bits can be used by software to decode the source of data.  The maximum data transfer width to internal memory is 32-bits, as in the case of PDAP data or I S and left-justified modes in single channel mode using 32 bits of data.
Page 537 Input Data Port Note that each input channel has its own clock and frame sync input, so unused IDP channels do not produce data and therefore have no impact on FIFO throughput. The clock and frame sync of any unused input should be routed by the SRU to low to avoid unintentional acquisition.
Page 538 Data Transfer S AND LEFT-JUSTIFIED FORMAT 24-BIT AUDIO DATA 3 BITS VALIDITY BIT IDP CHANNEL USER DATA L/R BIT CHANNEL STATUS BLOCK STATUS S AND LEFT-JUSTIFIED FORMAT, 32-BIT DATA WIDTH 32 BIT DATA Figure 11-8. IDP Data Buffer Format SIP – I2S/Left-Justified (32 Bits) The polarity of left-right encoding is independent of the serial mode frame sync polarity selected in for that channel...
Page 539 Input Data Port NO PACKING 1x20-BIT RESERVED PACKING BY 2 2x16-BIT 16 15 PACKING BY 3 TRI-WORD 21 20 PACKING BY 4 4x8-BIT Figure 11-9. IDP Data Buffer Formats for the PDAP DMA Transfers The processors support two types of DMA transfers, standard and ping-pong.
Page 540 Data Transfer DMA Channel Priority When more than one channel has data ready, the channels always access register with fixed priority, from low to high channel num- IDP_FIFO ber (that is, channel 0 is the highest priority and channel 7 is the lowest priority).
Page 541 Input Data Port Ping-Pong DMA In ping-pong DMA, the parameters have two memory index values (index A and index B), one count value and one modifier value. The DMA starts the transfer with the memory indexed by A. When the transfer is com- pleted as per the value in the count register, the DMA restarts with the memory location indexed by B.
Page 542 Data Transfer ping-pong DMA, initialize the corresponding IDP_DMA_IxA IDP_DMA_IxB registers. IDP_DMA_Mx IDP_DMA_PCx DMA transfers for all 8 channels can be interrupted by changing the bit in the register. None of the other control settings IDP_DMA_EN IDP_CTL0 (except for the bit) should be changed. Clearing the IDP_EN IDP_DMA_EN bit (= 0) does not affect the data in the FIFO, it only stops DMA transfers.
Page 543 Input Data Port These are sticky bits that must be cleared by writing to the IDP_CLROVR (bit 6 of the register). When an overflow occurs, incoming data IDP_CTL0 from IDP channels is not accepted into the FIFO, and data values are lost. New data is only accepted once space is again created in the FIFO.
Page 544 Interrupts DMA Interrupts Using DMA transfer overrides the mechanism used for interrupt-driven core reads from the FIFO. When the bit and at least one IDP_DMA_EN of the register are set, the eighth interrupt IDP_DMA_ENx IDP_CTL1 ) in the registers is NOT generated. IDP_FIFO_GTN_INT DAI_IMASK_x At the end of the DMA transfer for individual channels, interrupts are...
Page 545 Input Data Port Debug Features The following sections describe the features available for debugging the IDP. Status register Debug The core may also write to the FIFO. When it does, the audio data word is pushed into the input side of the FIFO (as if it had come from the SRU on the channel encoded in the three LSBs).
Page 546 Effect Latency Core FIFO Write The core may also write to the FIFO. When it does, the audio data word is pushed into the input side of the FIFO (as if it had come from the SRU on the channel encoded in the three LSBs). This can be useful for verify- ing the operation of the FIFO, the DMA channels, and the status portions of the IDP.
Page 547 Input Data Port Setting Miscellaneous Bits This sequence is used in most following programming models as interme- diate step. Set the required values for: • bits in the register to specify the frame sync IDP_SMODEx IDP_CTLx format for the serial inputs (left-justified I S, or right-justified mode).
Page 548 Programming Model 5. Set the desired values for the N_SET variable using the IDP_NSET bits in the register. IDP_CTL0 6. Set the bit (bit 8 of the register) IDP_FIFO_GTN_INT DAI_IMASK_RE to HIGH and set the corresponding bit in the regis- DAI_IMASK_FE ter to LOW to unmask the interrupt.
Page 549 Input Data Port 3. Wait for the DAI interrupt, and enable the IDP port inside the DAI interrupt service routine. 4. Clear the DAI interrupt by reading the DAI interrupt latch regis- ter. This procedure ensures that the IDP ports are enabled at the correct time, avoiding issues like channel shift or swap in the received data.
Page 550 Programming Model • The global bit (bit 7 in the register). IDP_EN IDP_CTL0 Starting a Ping-Pong DMA Transfer To start a ping-pong DMA transfer from the FIFO to memory: 1. Clear the FIFO by setting (= 1) the bit (bit 31 in the IDP_FFCLR register).
Page 551 Input Data Port Servicing Interrupts for DMA The following steps describe how to handle an IDP ISR for DMA. 1. An interrupt is generated and program control jumps to the ISR when the DMA for a channel completes. 2. The program clears the bit in the register.
Page 552 Programming Model 6. Re-enable the bit in the register (set to 1). IDP_DMA_EN IDP_CTL 7. Exit the ISR. If a zero is read in step 5 (no more interrupts are latched), then all of the interrupts needed for that ISR have been serviced. If another DMA com- pletes after step 5 (that is, during steps 6 or 7), as soon as the ISR completes, the ISR is called again because the OR of the latched bits will not be nonzero again.
Page 553 12 ASYNCHRONOUS SAMPLE RATE CONVERTER The asynchronous sample rate converter (SRC) block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using any internal processor resources. Further- more, the SRC is used to clean up audio data from jittery clock sources such as the S/PDIF receiver.
Page 554 Features Table 12-1. SRC Specifications (Cont’d) Feature Availability Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Yes (RAM, ROM) Clock Operation PCLK Features The SRC for the SHARC processors has the features shown in the list below.
Page 555 Asynchronous Sample Rate Converter • Linear phase FIR filter • Controllable soft mute Pin Descriptions The SRC has two interfaces: an input port and an output port. Table 12-2 describes the six inputs and two outputs for the IP (input port) and OP (output port).
Page 556 Register Overview Table 12-3. SRC DAI/SRU Signal Routing ADSP-214xx Internal Node DAI Connection SRU Register Inputs SRC3–0_CLK_IP_I Group A SRU_CLK2–1 SRC3–0_CLK_OP_I SRC3–0_FS_IP_I Group C SRU_FS2–1 SRC3–0_FS_OP_I SRC3–0_DAT_IP_I Group B SRU_DAT3–2 SRC3–0_TDM_OP_I Outputs SRC3–0_DAT_OP_O Group B, D SRC3–0_TDM_IP_O Group B For information on using the SRU, see “Rules for SRU Connections”...
Page 557 Asynchronous Sample Rate Converter Clocking The fundamental timing clock of the ASRC module is peripheral clock/4 /4) and is operating in slave mode only. PCLK Functional Description Figure 12-1 shows a top level block diagram of the SRC module and Figure 12-2 shows architecture details.
Page 558 Functional Description SRCCTL MUTE SRCMUTE S/PDIF RX INTERRUPT Auto/Manual Hard/Soft/Auto SRCx_TDM_IP_O MUTE MUTE SRCx_FS_IP_I 64-BIT SERIAL INPUT DE-EMPHASIS SAMPLE RATE SRCx_CLK_IP_I SHIFT PORT (SIP) FILTER CONVERTER SMODE IN (SRC) RATIO SRCx_DAT_IP_I PCLK/4 SRCx_DAT_OP_O SERIAL SRCx_FS_OP_I OUTPUT PORT (SOP) 64-BIT DITHER SHIFT SRCx_CLK_OP_I MATCHED PHASE...
Page 559 Asynchronous Sample Rate Converter RIGHT DATA IN ROM A HIGH FIFO LEFT DATA IN ROM B ORDER INTERPOLATION ROM C ROM D DIGITAL SRCx_FS_IP FIR FILTER SERVO LOOP COUNTER SRCx_DAT_OP SAMPLE RATE RATIO SRCx_FS_IP SAMPLE RATE SRCx_FS_OP RATIO EXTERNAL RATIO (MATCHED PHASE MODE) Figure 12-2.
Page 560 Functional Description rate, a fast mode has been added to the filter. When the digital-servo loop starts up or the sample rate is changed, the digital-servo loop kicks into fast mode to adjust and settle on the new sample rate. Upon sensing the digital-servo loop settling down to some reasonable value, the digital-servo loop kicks into normal or slow mode.
Page 561 Asynchronous Sample Rate Converter ratios, two SRCs may have differences in their ratios from 0 to 4 period counts. The ( ) ratio adjusts SRCx_FS_OP SRCx_FS_OP SRCx_FS_IP the filter length of the SRC, which corresponds directly with the group delay. Thus, the magnitude in the phase difference depends upon the res- olution of the counters.
Page 562 Operating Modes RIGHT CHANNEL LEFT CHANNEL LRCLK SCLK SDATA LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL LRCLK LEFT CHANNEL RIGHT CHANNEL SCLK SDATA I2S MODE – 16 BITS TO 24 BITS PER CHANNEL RIGHT CHANNEL LEFT CHANNEL LRCLK SCLK SDATA...
Page 563 Asynchronous Sample Rate Converter TDM Input Daisy Chain In TDM input port, several SRCs can be daisy-chained together and con- nected to the serial input port of a SHARC processor or other processor (Figure 12-4). The SRC IP contains a 64-bit parallel load shift register. When the pulse arrives, each SRC parallel loads its left and SRCx_FS_IP_I...
Page 564 Operating Modes TDM IP Daisy Chain Clock, FS MASTER SRC2_DAT_IP_I SRC1_DAT_IP_I SRC0_DAT_IP_I SRC2_TDM_IP_O SRC1_TDM_IP_O SRC0_TDM_IP_O SPORT_Dx_O SRC2_TDM_OP_I SRC1_TDM_OP_I SRC0_TDM_OP_I SPORT_Dx_I MASTER SRC2_DAT_OP_O SRC1_DAT_OP_O SRC0_DAT_OP_O Clock, FS TDM OP Daisy Chain Figure 12-4. TDM Input/Output Modes Bypass Mode When the bit is set (=1), the input data bypasses the sample rate BYPASS converter and is sent directly to the serial output port.
Page 565 Asynchronous Sample Rate Converter between two or more adjacent sample rate converters that are operating with the same input and output clocks. When the bit is set SRCx_MPHASE (=1), the SRC, a matched phase mode slave accepts the sample rate ratio transmitted by another SRC, the matched phase mode master, through its serial output as shown in Figure...
Page 566 Operating Modes cycles per subframe in matched-phase mode (24-bits data and 8-bits phase match). Data Format Matched-Phase Mode The SRC supports the matched-phase mode for all serial output data for- mats; left-justified, I S, right-justified, and TDM mode. Note that in the left-justified, I S, and TDM modes, the lower 8 bits of each channel sub- frame are used to transmit the matched-phase data.
Page 567 Asynchronous Sample Rate Converter     SRCx_FS_IP × ≤ ------------------------------ - -------------------------------- - ------------------------------ - onds for SRCx_FS_OP SRCx_FS_IP     SRCx_FS_IP SRCx_FS_OP SRCx_FS_IP Decimation Rate The RAM in the FIFO is 512 words deep for both left and right channels. An offset to the write address provided by the f _IN counter is added to prevent the RAM read pointer from ever overlapping the write address.
Page 568 Interrupts A 12-bit counter, clocked by , is used to control the mute SRCx_FS_IP_I attenuation. Therefore, the time it takes from the assertion of MUTE_IN –144 dB, full mute attenuation is 4096 FS cycles. Likewise, the time it takes to reach 0 dB mute attenuation from the deas- sertion of is 4096 FS cycles.
Page 569 Asynchronous Sample Rate Converter ratio. Hard mute, soft mute, and auto mute only control the muting of the input data to the SRC. Table 12-4 provides an overview of SRC interrupts. Table 12-4. SRC Interrupt Overview Interrupt Source Interrupt Condition Interrupt Interrupt Default IVT...
Page 570 Effect Latency SRC Effect Latency After the ASRC registers are configured the effect latency is 1.5 PCLK cycles minimum and 3 cycles maximum. PCLK 12-18 ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 571 13 SONY/PHILIPS DIGITAL INTERFACE The Sony/Philips Digital Interface (S/PDIF) is a standard audio data transfer format that allows the transfer of digital audio signals from one device to another without having to convert them to an analog signal. The digital audio interface carries three types of information; audio data, non audio data (compressed data) and timing information.
Page 572 Features Table 13-1. S/PDIF Specifications (Cont’d) Feature Transmitter Receiver Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation PCLK PCLK Features The S/PDIF interface has the following features. • AES3-compliant S/PDIF transmitter and receiver. •...
Page 573 Sony/Philips Digital Interface • DAI allows interactions over DAI by serial ports, IDP and/or the external DAI pins to interface to other S/PDIF devices. This includes using the receiver to decode incoming biphase encoded audio streams and passing them via the SPORTs to internal mem- ory for processing-or using the transmitter to encode audio or digital data and transfer it to another S/PDIF receiver in the audio system.
Page 574 SRU Programming Table 13-2. S/PDIF Transmitter Pin Descriptions (Cont’d) Internal Node Description DIT_O Output Transmit Biphase Mark Encoded Data Stream. DIT_BLKSTART_O Output Transmit Block Start. Indicates the last frame of the current block. This is high for the entire duration of the last frame.
Page 575 Sony/Philips Digital Interface clock, frame sync, data, and (if external synchronization is EXT_SYNC required) inputs also need to be routed through SRU (see Table 13-4). Table 13-4. S/PDIF DAI/SRU Transmitter Signal Connections Internal Node DAI Group SRU Register Inputs DIT_CLK_I Group A SRU_CLK4–2 DIT_HFCLK_I...
Page 576 Register Overview Table 13-5. S/PDIF DAI/SRU Receiver Signal Connections (Cont’d) Internal Node DAI Group SRU Register Outputs DIR_CLK_O Group A, D DIR_TDMCLK_O DIR_FS_O Group C, D DIR_DAT_O Group B, D DIR_LRCLK_FB_O Group D DIR_LRCLK_REF_O Register Overview This section provides brief descriptions of the major registers. For com- plete information see “Sony/Philips Digital Interface Registers”...
Page 577 Sony/Philips Digital Interface Receive Status Register (DIRSTAT). The receiver also detects errors in the S/PDIF stream. These error bits are stored in the status register, which can be read by the core. Optionally, an interrupt may be generated to notify the core on error conditions. Receive Channel Status Registers (DIRCHANAx/Bx).
Page 578 S/PDIF Transmitter off-board connections to other S/PDIF receivers. The output is also avail- able to the S/PDIF receiver for loop-back testing through SRU. In addition to encoding the audio data in the bi-phase format, the trans- mitter also provides a way to easily add the channel status information to the outgoing bi-phase stream.
Page 579 Sony/Philips Digital Interface 24-bit word widths. The over sampling clock is also selected by the trans- mitter control register. STATUS/USER BIT REGISTERS BLK_START_O LRCLK BLK_START INTERNAL LEFT DATA BUFFER TX_ENABLE SAMPLE BIT RIGHT DATA BIPHASE BIPHASE_OUT SAMPLE ENCODER U, V, CS LEFT U, V, CS RIGHT U, V, CS BITS EXT SYNC...
Page 580 S/PDIF Transmitter  When I S format is used with 20-bit or 16-bit data, the audio data should be placed from the MSB of the 24-bit audio data. Bits 27–4: 24-Bit Audio Data Validity Bit User Data Channel Status Block Start Figure 13-4.
Page 581 Sony/Philips Digital Interface Operating Modes The S/PDIF transmitter can operate in standalone and full serial modes. The following sections describe these modes in detail. Full Serial Mode This mode is selected by clearing bit 9 in the register. In this mode DITCTL all the status bits, audio data and the block start bit (indicating start of a frame), come through the serial data stream (...
Page 582 S/PDIF Transmitter To allow user bit updates, write a 0x1 to the register that is DIT_USRUPD used for further processing. If the bit in the register is DIT_AUTO DITCTL set: • At every 192nd Frame end, if = 1, then the user status DITUSRUPD bits are taken from user bits buffers and transmitted.
Page 583 Sony/Philips Digital Interface In SCDF mode, the transmitter sends successive audio samples of the same signal across both sub frames, instead of channel A and B. The trans- mitter will transmit at half the sample rate of the input bit stream. The bit (bit 4 in the register selects SCDF mode.
Page 584 S/PDIF Receiver PROCESSOR OFF-CHIP LRCLK_REF_O REFIN ANALOG DIGITAL LRCLK_FB_O FBIN PLLCLK SPDIF_EXTPLLCLK_I 512 x FS STREAM FEEDBACK DIVIDER = 512 PREAMBLE DIR_CLK_O DIR_FS_O BIPAHSE DIR_I DECODING (BIPHASE STREAM) REFRAMING DIR_DAT_O LOGIC DIR_TDMCLK_O S/PDIF RECEIVER Figure 13-8. S/PDIF Receiver Block Diagram The input to the receiver ( ) is a biphase encoded signal that may DIR_I...
Page 585 Sony/Philips Digital Interface start bit, which replaces the parity bit in the serial I S stream, indicates the reception of the Z preamble and the start of a new block of channel status and data bits. Clock Recovery The phased-locked loop for the AES3/SPDIF receiver is intended to recover the clock that generated the AES3/SPDIF biphase encoded stream.
Page 586 S/PDIF Receiver Channel Status The channel status for the first bytes 4–0 (consumer mode) are collected into memory-mapped registers ( registers). DIRCTL DIRCHANA DIRCHANB All other channel status bytes 23–5 (professional mode) must be manually extracted from the receiver data stream. ...
Page 587 Sony/Philips Digital Interface detected, the bit flag is set. If the sync code is not detected DIR_NOAUDIO again within 4096 frames, the bit flag is deasserted. DIR_NOAUDIO The last two words of the sync code, 0xF872 and 0x4E1F, are called the preamble-A and preamble-B of the burst preamble.
Page 588 S/PDIF Receiver Single-Channel Double-Frequency Mode Single-channel, double-frequency mode (SCDF) mode is selected with bits in the register. The DIR_SCDF DIR_SCDF_LR DIRCTL DIR_B0CHANL/R bits in the register also contain information about the SCDF DIRSTAT mode. When the indicates single channel double frequency DIR_B0CHANL mode, the two subframes of a frame carry successive audio samples of the same signal.
Page 589 Sony/Philips Digital Interface External Analog PLL Notice there are various performance characteristics to consider when con- figuring for analog PLL mode. In order to provide the receiver with an external PLL the appropriate routings needs to be performed including the setting of bit which disables the internal PLL and connects to DIR_PLLDIS...
Page 590 Interrupts Receiver Interrupts The following three receiver status bits ( ) generate an DAI_IRPTL_x interrupt. • No audio ( DIR_NOAUDIO_INT • Emphasized audio ( DIR_EMPHASIS_INT • Status change ( DIR_STATCNG_INT Note the Status change interrupt is generated if any of the 40 status bits (bytes 4–0) have changed.
Page 591 Sony/Philips Digital Interface Debug Features The following feature supports S/PDIF debugging. Loop Back Routing The S/PDIF supports an internal loopback mode by using the SRU. more information, see “Loop Back Routing” on page 9-40. Effect Latency The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).
Page 592 Programming Model desired mode in the transmitter control register. This setup can be accom- plished in three steps. 1. Connect the transmitter’s four required input signals and one biphase encoded output in the SRU. The four input signals are the serial clock ( ), the serial frame sync ( ), the serial...
Page 593 Sony/Philips Digital Interface ), the serial frame sync ( ), and the serial data DIR_CLK_O DIR_FS_O ). The high frequency clock ( ) derived DIR_DAT_O DIR_TDMCLK_O from the encoded stream is also available if the system requires it. 2. Initialize the register to enable the data decoding.
Page 594 Programming Model bit set imask DAIHI; ustat1 = DIR_NOSTREAM_INT; /* Enable no-stream Interrupt on Falling Edge. Interrupt occurs when the stream is reconnected */ dm(DAI_IRPTL_FE) = ustat1; /* Enable Hi-priority DAI interrupt */ dm(DAI_IRPTL_PRI) = ustat1; /* If more than 1 DAI interrupt is being used, it is neces- sary to determine which interrupt occurred here */ /* Interrupt Service Routine for the DAI Hi-Priority Inter- rupt.
Page 595 14 PRECISION CLOCK GENERATOR The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A B, C, and D, are identical in functionality and operate independently of each other.
Page 596 Features Table 14-1. PCG Specifications (Cont’d) Feature PCGA–B PCGC–D Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation PCLK PCLK Features The following list describes the features of the precision clock generators. •...
Page 597 Precision Clock Generator • Bypass mode for external frame sync manipulation • External trigger mode starts PCG operation. No additional jitter introduced since operation is independent of the on-chip PLL by using off-chip clocks. Pin Descriptions Table 14-2 provides the pin descriptions for the PCGs. Note x = unit A/B/C/D.
Page 598 SRU Programming SRU Programming To use the PCG, route the required inputs using the SRU as described Table 14-3. Also, use the SRU to connect the outputs to the desired DAI pin. Table 14-3. PCG DAI/SRU Connections Internal Nodes DAI Group DPI Group SRU Register Inputs...
Page 599 Precision Clock Generator PCG C and D cannot be directly connected to other peripheral clock and frame sync signals. They can only be routed through the DAI pins. Register Overview The processor contains registers that are used to control the PCGs. •...
Page 600 Functional Description Functional Description The following sections provide information on the function of the preci- sion clock generators. PCG_SYNC_CLKx_I Ext. Event Trigger SCLK Normal (>1) Bypass (0,1) CLKIN PCG_ CLKABCD_O CLKDIV FRAME SYNC PCLK PULSE WIDTH PHASE Normal (>1) PCG_ FSABCD_O FSDIV Bypass (0,1)
Page 601 Precision Clock Generator can theoretically run at up to the frequency. However the DAI/DPI PCLK pin buffers limit the speed to PCLK Note that the clock output is always set (as closely as possible) to a 50% duty cycle. If the clock divisor is even, the duty cycle of the clock output is exactly 50%.
Page 602 Functional Description Divider Mode Selection If frame sync divisor > 1 the PCG frame sync output frequency is equal to the input clock frequency, divided by a 20-bit integer. This integer is specified in the bit field (bits 19–0 of the register).
Page 603 Precision Clock Generator The phase shift between clock and frame sync outputs may be pro- grammed using the registers under these PCG_PW PCG_CTLxx conditions: • The input clock source for the clock generator output and the frame sync generator output is the same. •...
Page 604 Functional Description than the divisor of the frame sync. The pulse width of frame sync is speci- fied in the bits (15–0) and (31–16) of the registers. PWFSx PCG_PWx Default Pulse Width If the pulse width count is equal to 0 and if bit field is even, then FSDIV the actual pulse width of the frame sync output is equal to:...
Page 605 Precision Clock Generator Timing Example for I2S Mode For I S mode, the frame sync should be driven at the falling edge of SCLK In other words, the frame sync edge should coincide with the falling edge of the . To satisfy this requirement, the phase of the frame sync SCLK should be programmed accordingly in the registers.
Page 606 Operating Modes Normal Mode When the frame sync divisor is set to any value other than zero or one, the PCGs operates in normal mode. In normal mode, the frequency of the frame sync output is determined by the divisor where: Input Frequency Frequency of Frame Sync Output = Divisor...
Page 607 Precision Clock Generator Bypass Mode When the frame sync divisor for the frame sync has a value of zero or one, the frame sync is in bypass mode, and the registers have different PCG_PWx functionality than in normal mode.  In normal mode bits 15–0 and 31–18 of the registers are PCG_PWx...
Page 608 Operating Modes In the bypass mode, if the bit of register is set to 1, then STROBEx PCG_PWx a one-shot pulse is generated. This one-shot pulse has the duration equal to the period of for the PCGx unit. This pulse is generated MISCAx_I either at the falling or rising edge of the input clock, depending on the value of the...
Page 609 Precision Clock Generator Since the rising edge of the external clock is used to synchronize with the frame sync, the frame sync output is not generated until a rising edge of the external clock is sensed (Figure 14-5). TRIGGER DELAY CLKIN (INPUT) EXT.
Page 610 Operating Modes • SRU is the input source. If the input clock and trigger signal are synchronous, the delay is exactly 3 input clock periods. If asyn- chronous, it varies between 2.5 to 3.5 input clock periods depending on the phase difference between the input clock and trigger signal.
Page 611 Precision Clock Generator FS OUT = 65.1 kHz 24-BIT ADSP-214xx LEFT-JUSTIFIED PLAYER SDATA OUT DAI_P8 RxSCLK DAI_P19 SDATA IN DAI_P9 RxLRCLK SPDIF LRCLK IN SPDIF IN ASRC SDATA IN DAI_P10 (FS IN , 44.1 kHz) SCLK IN FSYNC A (FS OUT ) PCG_ FSA_O STEREO DAC...
Page 612 Operating Modes Set the clock divisor and source and low-phase word first, followed by the control register enable bits, which must be set together. When the PCG_PW register is set to zero (default) the FS pulse width is (divisor ÷ 2) for even divisors and (divisor –...
Page 613 Precision Clock Generator For more information on core clock setting, see “ADSP-2146x Power Management Registers” on page A-6 “ADSP-2147x/ADSP-2148x Power Management Registers” on page A-12. Effect Latency The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).
Page 614 Programming Model Input clock through SRU • If divisor is 0 or 1 (bypassed) the latency can vary from 0 to 1 input clock period. For example if the input clock has a period of 100 ns then this latency can be a maximum of 100 ns. •...
Page 615 Precision Clock Generator Programming should occur in the following order. 1. Program the and the registers PCG_SYNC PCG_CTLA0–1 PCG_CTLB0–1 appropriately. 2. Enable clock or frame sync, or both. Since the rising edge of the external clock is used to synchronize with the frame sync, the frame sync output is not generated until a rising edge of the external clock is sensed.
Page 616 Debug Features 14-22 ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 617 15 SERIAL PERIPHERAL INTERFACE PORTS The ADSP-214xx processors are equipped with two synchronous serial peripheral interface ports that are compatible with the industry-standard serial peripheral interface (SPI). Each SPI port also has its own set of regis- ters (the secondary register set contains a B as in ).
Page 618 Features Table 15-1. SPI Port Specifications (Cont’d) Feature SPI/SPIB Transmission Full Duplex Yes (Core and DMA) Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Interrupt Source Core/DMA Boot Capable Local Memory Clock Operation /4 (slave) f /8 (master) PCLK PCLK...
Page 619 Serial Peripheral Interface Ports • Programmable baud rates, clock polarities, and phases (SPI mode 0–3). • Master or slave booting from a master SPI device. See “SPI Port Booting” on page 23-12. • DMA capability to allow transfer of data without core overhead. “DMA Transfers”...
Page 620 SRU Programming Table 15-2. SPI Pin Descriptions (Cont’d) Internal Node Type Description SPI_MOSI_I/O SPI Master Out Slave In. This data line transmits the output data SPIB_MOSI_I/O from the master device and receives the input data to a slave device. This data is shifted out from the MOSI pin of the master and shifted into the MOSI input(s) of the slave(s).
Page 621 Serial Peripheral Interface Ports Table 15-3. SPI DPI/SRU2 Signal Connections Internal Node DPI Group SRU2 Register Inputs SPI_CLK_I Group A SRU2_INPUT1–0 SPIB_CLK_I SPI_DS_I SPIB_DS_I SPI_MOSI_I SPIB_MOSI_I SPI_MISO_I SPIB_MISO_I Outputs SPI_CLK_O Group B SPIB_CLK_O SPI_MOSI_O SPIB_MOSI_O SPI_MISO_O SPIB_MISO_O SPI_FLG3–0_O SPIB_FLG3–0_O SPI_CLK_PBEN_O Group C SPIB_CLK_PBEN_O SPI_MOSI_PBEN_O...
Page 622 Clocking SPI Control (SPICTLx). This register configures the fundamental trans- fer initiation mode (core or DMA) and configure timing bits and enable the SPI port. SPI DMA Control (SPIDMACx). This register control the DMA channel on SPI and corresponding status bits provide status or error information on transmission.
Page 623 Serial Peripheral Interface Ports Table 15-4. SPI BAUD Rate – PCLK = 200 MHz (Cont’d) BAUDR Bit Setting Divider SPICLK 12.5 2.0 (master boot) 32,767 131068 1526 Hz Choosing the Pin Enable for the SPI Clock When using the SPI in master mode, and the signal is routed SPIxCLK onto the DPI pin, then the...
Page 624 Functional Description connected to high, as it affects the functioning of certain bits in the register. SPICTLx Functional Description Each SPI interface contain its own transmit shift ( ) and receive TXSR TXSRB shift ( ) registers (not user accessible). The registers seri- RXSR RXSRB...
Page 625 Serial Peripheral Interface Ports transmitted is irrelevant. A 4-word deep FIFO is included to improve throughput on the IOD0 bus. SPIx_MOSI_I/O SPIx_MISO_I/O SPIx_DS_I SPIx_FLG_3-0_O SPIx_CLK_I/O SPI CONTROL/STATUS RXSR SHIFT REGISTER TXSR SHIFT REGISTER 8/16/32 BITS 8/16/32 BITS TXSPI REGISTER RXSPI REGISTER 1 DEEP 1 DEEP DMA FIFO...
Page 626 Functional Description However, the starts toggling after a delay equal to one-half (0.5) SPICLK period. For a slave with = 0, the transfer starts as soon SPICLK CPHASE as the input transitions to low. SPI_DS_I = 1, a transfer starts with the first active edge of CPHASE SPICLK both slave and master devices.
Page 627 Serial Peripheral Interface Ports a AD1855 STEREO 96 kHz DAC ADSP-214xx DPI (SPI_CLK_O) CCLK CLATCH DPI (SPI_FLG0_O) DPI (SPI_MOSI_O) DATA MASTER DEVICE Figure 15-3. SHARC Processor as SPI Master Multi Master Systems The SPI does not have an acknowledgement mechanism to confirm the receipt of data.
Page 628 Operating Modes BUS ARBITRATION LOGIC SPIFLGxy SPI_DS_I SPIFLGxy SPI_DS_I SPIFLGxy SPI_DS_I SPI #1 SPI #2 SPI #3 SPICLK SPI_MOSI_PBEN_O (open drain) SPI_MISO_PBEN_O (open drain) Figure 15-4. Multi Master System pins to the DPI pins of the master SHARC. Since these flags are SPIDS NOT open drain, slave select pins cannot be shorted together in multi master environment.
Page 629 Serial Peripheral Interface Ports Transfer Initiate Mode When the processor is enabled as a master, the initiation of a transfer is defined by the bits (1–0). Based on these two bits and the status of TIMOD the interface, a new transfer is started upon either a read of the reg- RXSPIx isters or a write to the...
Page 630 Operating Modes SPI Modes The SPI supports four different combinations of serial clock phases and polarity called SPI modes. The application code can select any of these combinations using the bits (10 and 11). CLKPL CPHASE Figure 15-5 on page 15-15 shows the transfer format when = 0 and CPHASE...
Page 631 Serial Peripheral Interface Ports CLOCK CYCLE# SPI_CLK_O CLKPL=0 (SPI MODE 0) SPI_CLK_O CLKPL=1 (SPI MODE 2) SPI_MOSI_O FROM MASTER SPI_MISO_I FROM SLAVE SPI_FLG_I FROM MASTER * = UNDEFINED Figure 15-5. SPI Transfer Protocol for CPHASE = 0 Figure 15-6 shows the SPI transfer protocol for = 1.
Page 632 Operating Modes CLOCK CYCLE# SPI_CLK_O CLKPL=0 (SPI MODE 1) SPI_CLK_O CLKPL=1 (SPI MODE 3) SPI_MOSI_O FROM MASTER SPI_MISO_O FROM SLAVE SPI_DS_I TO MASTER * = UNDEFINED Figure 15-6. SPI Transfer Protocol for CPHASE = 1 asserted (active-low) between transfers or be deasserted between transfers. This is controlled in software using the bits ( register).
Page 633 Serial Peripheral Interface Ports Variable Frame Delay for Slave When the processor is configured as an SPI slave, the SPI master must drive an signal that conforms with Figure 15-7. For exact timing SPICLK parameters, please refer to the appropriate product data sheet. As shown in Figure 15-7, the...
Page 634 Data Transfers SPI_CLK_I CPHASE=0 SPI_DS_I TO SLAVE Figure 15-7. SPICLK Timing When word to word delay is enabled ( = 1) in the register, WTWDEN SPICTL then T3 may vary with respect to the value programmed using the STDC bits in the register.
Page 635 Serial Peripheral Interface Ports in the registers are zeros. This code works only if the bit is zero in MSBF both the transmitter and receiver, and the frequency is less. If SPICLK MSBF = 1 in the transmitter and receiver, and has a lower frequency, the SPICLK received words follow the order 0x12, 0x34, 0x56, 0x78.
Page 636 Data Transfers • If = 0 and the receive buffer is full, the incoming data is discarded, and the register is not updated. RXSPI 2. If core access to a SPI master is unable to keep up with the trans- mit/receive stream during a transfer operation (because of an interrupt or another reason) the SPI stalls the until new...
Page 637 Serial Peripheral Interface Ports transfer occurs when the bit is set. This indicates that a new word has been received and latched into the receive buffer, . The bit is set RXSPI shortly after the last sampling edge of . There is a 4 cycle SPICLK PCLK...
Page 638 Data Transfers When enabled as a master, the DMA engine transmits or receives data as follows: • If the SPI system is configured for transmitting, the DMA engine reads data from memory into the DMA FIFO. Data from the DMA FIFO is loaded into the buffer and then into the TXSPIx transmit shift register.
Page 639 Serial Peripheral Interface Ports DMA Chaining The serial peripheral interfaces support both single and chained DMA. However, unlike the serial ports, programs cannot insert a TCB in an active chain. For more information, see “SPI TCB” on page 2-14. Configuring and starting chained DMA transfers over the SPI port is the same as for the serial ports, with one exception.
Page 640 Interrupts Full Duplex Operation The SPI interface allows full-duplex operation running the DMA channel to the transmit/receive path and core access to the alternate trans- mit/receive path. For full-duplex operation, set = 10 which TIMOD generates the interrupts for DMA only. Reads from the buffer are allowed at any time during transmit RXSPIx...
Page 641 Serial Peripheral Interface Ports Table 15-7. SPI Interrupt Overview Interrupt Source Interrupt Condition Interrupt Completion Interrupt Default Acknowledge SPI (SPI Mode – DMA RX/TX done Internal transfer completion RTI instruction P1I, 3–0, 2 channels) – Core RX buffer full for core mode of operation. P18I –...
Page 642 Interrupts (bit 12) in the register. To service the secondary SPI port, unmask IMASK (set = 1) the bit (bit 19) in the register. For a list of these SPILIMSK LIRPTL bits, see the SHARC Processor Programming Reference. When using DMA transfers, programs must also specify whether to gener- ate interrupts based on transfer or error status.
Page 643 Serial Peripheral Interface Ports 2. The control bit in is cleared, disabling the SPI SPIEN SPICTL system. 3. The status bit in is set. SPISTAT 4. An SPI interrupt is generated. These four conditions persist until the bit is cleared by a write 1-to-clear (W1C-type) software operation.
Page 644 Effect Latency from , but their contents are identical to that of . When RXSPI RXSPI RXSPI is read from core, the bit is cleared (read only-to-clear) and an SPI transfer may be initiated (if = 00). No such hardware action occurs TIMOD when the shadow register is read.
Page 645 Serial Peripheral Interface Ports Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference. SPI Effect Latency After the SPI registers are configured the effect latency is 2 cycles to PCLK enable and 2 cycles to disable. PCLK Programming Model The section describes which sequences of software steps are required to get...
Page 646 Programming Model Then the program can change the SPI configuration. In this case, the slave is always selected. Data corruption can be avoided by enabling the slave only after configuring both the master and slave devices. Master Mode Transfers For core or DMA transfers, when the SPI is configured as a master, the ports should be configured and transfers started using the following steps: 1.
Page 647 Serial Peripheral Interface Ports Core Master Transfers When a device is to be used as a master, configure the ports using the fol- lowing procedure. 1. Initiate the SPI transfer by writing or reading to/from SPI buffers. The trigger mechanism for starting the transfer is dependant upon bits in the registers.
Page 648 Programming Model Slave Mode Transfers When the SPI is configured as a master, regardless of core or DMA the SPI ports should be configured and transfers started using the following steps. 1. Route all required signals ( ) for slave mode MOSI MISO SPICLK...
Page 649 Serial Peripheral Interface Ports DMA Slave Transfers To configure the SPI port for slave mode DMA transfers: 1. Define DMA receive (or transmit) transfer parameters by writing to the , and registers. IISPIx IMSPIx CSPIx 2. Write to the register to enable the SPI DMA engine SPIDMACx , bit 0).
Page 650 Programming Model receive DMA the status bit is asserted when the DMA count becomes zero. For transmit DMA the goes high when: SPIFE • the DMA count becomes zero and • the DMA FIFO becomes empty and • the buffer becomes empty ( bit high) and SPITX •...
Page 651 Serial Peripheral Interface Ports With enabled SPI: 1. Poll the bit in the register. If this bit is high the SPI SPIFE SPISTAT buffer can be cleared. 2. Clear the buffers and the buffer status without dis- RXSPIx TXSPIx abling the SPI. This can be done by ORing 0xC0000 with the present value in the register.
Page 652 Programming Model 3. Disable DMA and clear the DMA FIFO by setting the FIFOFLSH bit is the registers. This ensures that any data from a pre- SPIDMACx vious DMA operation is cleared because the signal runs for SPICLK five more word transfers even after the DMA count falls to zero in the receive DMA.
Page 653 Serial Peripheral Interface Ports 5. Reconfigure the registers to remove the clear condition on SPICTLx registers. TXSPIx RXSPIx 6. Configure DMA by writing to the DMA parameter registers and registers using the bit (bit 0). SPIDMACx SPIDEN DMA Error Interrupts bits of the registers indicate transmission SPIUNF...
Page 654 Programming Model With SPI enabled: 1. Disable DMA and clear the DMA FIFO by bit in the FIFOFLSH register. This ensures that any data from a previous DMA SPIDMACx operation is cleared before configuring a new DMA operation. 2. Clear the registers and the buffer status without dis- RXSPIx TXSPIx...
Page 655 Serial Peripheral Interface Ports 5. If bus requester detects the pin high, it sets the SPI_DS_I SPIMS to get bus mastership. 6. The master selects a slave by driving its’ slave select flag pin. ADSP-214xx SHARC Processor Hardware Reference 15-39 www.BDTIC.com/ADI...
Page 656 Programming Model 15-40 ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 657 16 PERIPHERAL TIMERS In addition to the internal core timer, the ADSP-214xx processors contain identical 32-bit peripheral timers that can be used to interface with exter- nal devices. Each timer can be individually configured in three operation modes. The timers specifications are shown in Table 16-1.
Page 658 Features Table 16-1. Timer Specifications (Cont’d) Feature Timer1–0 DMA Chaining Interrupt Source Core Boot Capable Local Memory Clock Operation PCLK Features The peripheral timers have the features described below. • Independent general-purpose timers • Three operation modes (PWM, Width capture, external watchdog) •...
Page 659 Peripheral Timers Pin Descriptions The timer has only one pin which acts as input or output based on the timer mode as shown in Table 16-2. Table 16-2. Peripheral Timer Pin Descriptions Internal Node Type Description TIMER1–0_I Timer Signal. This input is active sampled during pulse width and period capture (width capture mode) or external event watchdog (external clock mode).
Page 660 Register Overview Register Overview The following sections provide brief descriptions of the primary registers used to program the timers. For information on the timer registers, see “Peripheral Timer Registers” on page A-269. Status and Control Registers (TMSTAT). The ( ) register indicates TMSTAT the status of both timers using a single read.
Page 661 Peripheral Timers During the external event watchdog (EXT_CLK) mode, the period register is write-only. Therefore, the period buffer is used in this mode to insure high/low period value coherency. Pulse Width Register (TMxW). During the pulse width modulation (PWM_OUT), the width value is written into the timer width registers. Both width and period register values must be updated “on the fly”...
Page 662 Functional Description pins through the signal routing unit (SRU). The timer signal functions as an output signal in PWM_OUT mode and as an input signal in WDTH_CAP and EXT_CLK modes. To provide these functions, each timer has four, 32-bit registers shown in Figure 16-1.
Page 663 Peripheral Timers When clocked internally, the clock source is the processor’s peripheral clock ( ). The timer produces a waveform with a period equal to 2 x PCLK and a width equal to 2 × . The period and width are set TMxPRD TMxW through the...
Page 664 Operating Modes Table 16-4. Timer Signal Use (Cont’d) Register PWM_OUT Mode WIDTH_CAP Mode EXT_CLK Mode Settings TMxOVF Set if Initialized with: Set if the Counter wraps Unused (IRQ also set) Period < Width or (Error Condition) Period == Width or Period == 0 TMxIRQ If PERIOD_CNT:...
Page 665 Peripheral Timers • Period value is lower than width value • Width is equal to period CORE BUS TIMERx_PERIOD TIMERx_WIDTH TIMERx_COUNTER PCLK RESET EQUAL? EQUAL? TIMER_ENABLE ASSERT DEASSERT INTERRUPT PWMOUT PULSE LOGIC TIMERx_O PERIOD_CNT Figure 16-2. Timer Flow Diagram – PWM_OUT Mode On invalid conditions, the timer sets both the and the TIMxOVF...
Page 666 Operating Modes PCLK PERIOD WIDTH cycle W_BUF X = P - W cycle cycle P_BUF W - 1 COUNTER X - 1 ZERO cycle TIMERx_O cycle Figure 16-3. PWM_OUT Timing PWM Waveform Generation If the bit is set, the internally-clocked timer generates rectangular PRDCNT signals with well-defined period and duty cycles.
Page 667 Peripheral Timers To control the assertion sense of the signal, the bit in the TIMERx_O PULSE corresponding register is either cleared (causes a low assertion TMxCTL level) or set (causes a high assertion level). When enabled, a timer interrupt is generated at the end of each period. An ISR must clear the interrupt latch bit and might alter period TIMxIRQ...
Page 668 Operating Modes is generated on the signal. If the bit is not set, the pulse is TIMERx_O PULSE active low. Pulse Mode The waveform produced in PWM_OUT mode with = 1 normally PRDCNT has a fixed assertion time and a programmable deassertion time (via the register).
Page 669 Peripheral Timers registers are read-only in WDTH_CAP mode. The period and pulse width ÷ 2. measurements are with respect to a clock frequency of PCLK Figure 16-5 shows a flow diagram for WDTH_CAP mode. In this mode, the timer resets words of the count in the register value to TMxCNT 0x0000 0001 and does not start counting until it detects the leading edge...
Page 670 Operating Modes The count registers are reset to 0x0000 0001 again, and the timer contin- ues counting until it is either disabled or the count value reaches 0xFFFF FFFF. In this mode, programs can measure both the pulse width and the pulse period of a waveform.
Page 671 Peripheral Timers PCLK TIMERx_I synchronized cycle W - 1 W + 1 P - 2 P - 1 COUNTER W_BUF cycle P_BUF cycle PERIOD cycle WIDTH cycle Figure 16-6. WDTH_CAP Timing (Period Count = 1) External Event Watchdog Mode (EXT_CLK) Figure 16-7 shows a flow diagram for EXT_CLK mode.
Page 672 Operating Modes After the timer is enabled, it waits for the first rising edge on the TIMERx_I signal. The rising edge forces the count register to be loaded by the value (0xFFFF FFFF – ). Every subsequent rising edge increments the TMxPRD count register.
Page 673 Peripheral Timers TIMERx_I PERIOD cycle P_BUF cycle P - 1 P - 2 P - 1 P - 2 COUNTER sync delay Figure 16-8. EXT_CLK Timing Interrupts This section describes all relevant registers and hardware to raise and ser- vice interrupts. Table 16-5 provides an overview of timer interrupts.
Page 674 Interrupts source without reference to the timer’s interrupt signal. The regis- TMSTAT ter contains an interrupt latch bit ( ) and an overflow/error TIMxIRQ indicator bit ( ) for each timer. TIMxOVF These sticky bits are set by the timer hardware and may be watched by software.
Page 675 Peripheral Timers Watchdog Functionality Any of the timers can be used to implement a watchdog functionality that can be controlled by either an internal or an external clock source. For a program to service the watchdog, the program must reset the timer value by disabling and then re-enabling the timer.
Page 676 Effect Latency Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference. Peripheral Timers Effect Latency After the timer registers are configured the effect latency is 3 cycles PCLK enable and 2 cycles disable. The timer starts 3 cycles after the PCLK PCLK...
Page 677 Peripheral Timers Programming Model The section describes which sequences of software steps are required to get the peripheral working successfully. To enable an individual timer, set the timer’s bit in the reg- TIMxEN TMSTAT ister. To disable an individual timer, set the timer’s bit in the TIMxDIS register.
Page 678 Programming Model 3. Set the bit. The timer performs boundary exception checks TIMEN on the period and width values: • If (width == 0 or Period < width or period == width) both bits are set. OVF_ERR • If there are no exceptions, the width value is loaded into the counter and it starts counting.
Page 679 Peripheral Timers 2. The bit determines when the status bit (if enabled) is PRDCNT set. • If ( == 1), is set when the period expires and the PRDCNT value is captured. • If ( == 0), is set when the width expires and the PRDCNT value is captured.
Page 680 Programming Model 2. Initialize the period register with the value of the maximum exter- nal count. 3. Set the bit. This loads the period value in the counter and TIMEN starts the count down. When the period expires, it is reloaded with the period value and the cycle repeats.
Page 681 17 SHIFT REGISTER – ADSP-2147X ADSP-2147x processors incorporate an 18 stage serial in, serial/parallel out Shift Register (SR). The serial in–serial out mode can be used to delay the serial data by a fixed amount of time. The serial output can also be used to cascade the shift register modules on two or more processors.
Page 682 Features Table 17-1. Shift Register Specifications (Cont’d) Feature Availability Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation PCLK Features The following list describes the features of the shift register. •...
Page 683 Shift Register – ADSP-2147x Pin Descriptions The pin descriptions for the shift register are described in the ADSP-2147x data sheet. SRU Programming To use the shift register, route the required inputs using the SRU as described in Table 17-2, taking not of the following. •...
Page 684 Register Overview The shift register input pins ( ) are routed by SR_CLK_I SR_LAT_I SR_SDI_I default to the external shift register pins ( SR_CLK SR_LAT SR_SDI Register Overview The processor contains registers that are used to control the shift register. •...
Page 685 Shift Register – ADSP-2147x Functional Description The Shift Register module consists of an 18-stage serial shift register, 18-bit latch, and three-state output buffers. Three-state buffers are imple- mented in I/O buffers. The shift register and latch have separate clocks. Data is shifted on the positive-going transitions of the input.
Page 686 Operating Modes SW RESET SR RESET HW RESET SR_CTL[6-2] DAI_PB08-01_O SR_SDO SR_SCLK_I 18-STAGE SHIFT REGISTER SR_SDI_I PCG_CLKA_O PCG_CLKB_O PCG_FSA_O PCG_FSB_O SR_LAT_I SR_SDI* SR_LDO[17-0] 18-BIT SR_SCLK* LATCH SR_LAT* SPx_DA/DB_O SHIFT REGISTER BLOCK SPx_FS_O SR_CTL[0] SPx_CLK_O I/O BUFFERS *DEDICATED EXTERNAL PINS (NOT DAI/DPI PINS) Figure 17-1.
Page 687 Shift Register – ADSP-2147x SR_SDCLK SR_SDI SR_LAT RESET/ SR_CTL1/ SR_CLR SR_LDOE SR_LDO 0x00003 0x00006 0x0000D 0x0001A 0x00035 0x0006A 0x000D6 SR_SDO (LSB) Figure 17-2. Shift Register Timing Parallel Data Output If the bit in the register is set, the output stage of the par- SR_LDOE SR_CTL allel data latch is enabled.
Page 688 Effect Latency Effect Latency The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific). Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference. Shift Register Effect Latency After the SR register is configured, the maximum effect latency is 2 PCLK...
Page 689 18 REAL-TIME CLOCK— ADSP-2147X The ADSP-2147x processors contain a real-time clock (RTC) which pro- vides a set of digital watch features to the processor, including time of day, alarm, and stopwatch countdown. It is typically used to implement either a real-time watch or a life counter. The RTC specifications are shown in Table 18-1.
Page 690 Table 18-1. RTC Specifications (Cont’d) Feature Availability Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation PCLK Features The RTC interface has the following features. • Provides a 1 Hz clock with Second, Minute, Hour and Day Coun- ter (0 to 32767 days) •...
Page 691 Real-Time Clock—ADSP-2147x Pin Descriptions The pins used for the real-time clock are described in the ADSP-2147x data sheet. Clocking The RTC timer is clocked by a 32.768 kHz crystal external to the proces- sor. The RTC system registers are clocked by this crystal. There is no way to disable the RTC counters from software.
Page 692 Functional Description Initialization Status Register (RTC_INITSTAT). Used to report initial- ization events. Functional Description The primary function of the RTC is to maintain an accurate day count and time of day. The RTC accomplishes this by means of four counters: •...
Page 693 Real-Time Clock—ADSP-2147x 24 HOURS HOURS MINUTES SECONDS EVENT EVENT EVENT EVENT 1 Hz RTXI TICK DAYS HOURS MINUTES SECONDS 32.768 kHz COUNTER COUNTER COUNTER COUNTER EQUAL? EQUAL? EQUAL? EQUAL? WRITE RTC_SWCNT RTC_ALARM REGISTER STOPWATCH COUNTER ALARM EVENT DAY ALARM NORMAL EVENT COUNTDOWN EQUAL 0?
Page 694 Functional Description the external battery or I/O supply) and is active irrespective of the status of the processor core supply (V ). When the processor core and I/O DDINT supply are valid: • the current time is updated every second into the RTC clock regis- ter ( RTC_CLOCK •...
Page 695 Real-Time Clock—ADSP-2147x RTC CORE VOLTAGE LEVEL SHIFTER RTC CONTROL I/O TO CORE INTERRUPT CONTROL Shadow Registers, RTC I/O VOLTAGE Interrupts and Status Read/Write Logic ALARM COUNTER DM/PM BUS OSCILLATOR 0 OSCILLATOR 1 POWER SWITCHING CIRCUITRY Figure 18-2. Functional Partitioning Operating Modes The following sections provide information on the operating modes avail- able to the real-time clock.
Page 696 Functional Description interrupt is enabled, the RTC generates an interrupt on the day and time specified. The alarm interrupt and day alarm interrupt can be enabled or disabled independently. Stopwatch The RTC provides a stopwatch function that acts as a countdown timer. The application can program a second count into the RTC Stopwatch Count register ( ).
Page 697 Real-Time Clock—ADSP-2147x As a second example, if there is a +50 ppm error in the 1Hz frequency, this also translates into 86400 × 50ppm seconds (=–4.32 seconds) error at the end of the day which in this case the time has to be subtracted. This is corrected in the RTC by counting 00:00:00 to 00:00:03 twice, so that the time is effectively subtracted.
Page 698 Interrupts In order to perform calibration on the bench, use the pin and RTCXTALIN check the ppm deviation from 32.768 KHz. This ppm error is same as in the internal 1Hz clock and the calibration register should be updated with the corresponding values as explained above.
Page 699 Real-Time Clock—ADSP-2147x • On countdown from a programmable value • Daily at a specific time • On a specific day and time • On a 1 Hz clock failure • Completion on pending writes to any 1 Hz registers Service Interrupts In the service routine the register should be read to identify the RTC_STAT...
Page 700 Interrupts Emulation Considerations An emulation halt can optionally mask all RTC interrupts by setting the bit in register. EMU_INTDIS RTC_CTL Effect Latency The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific). Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference.
Page 701 Real-Time Clock—ADSP-2147x  To ensure that writes between the core voltage and RTC voltage domain are properly synchronized, all write commands should be issued immediately after a seconds’ event in the register. RTC_STAT This two step sequence results in a write latency of up to 1 second. While the write sequence is ongoing, the write pending ( ) bit is set in the WR_PEND...
Page 702 Interrupts This sequence applies only to the first time the RTC supply (bat- tery or I/O) is connected. Once the bit is set or reset, its RTCPDN value is retained as long as RTC supply (battery or I/O) is valid. 3.
Page 703 Real-Time Clock—ADSP-2147x the value written to . Wait for the writes to complete on RTC_CLOCK these registers before using the flags and interrupts associated with their values. The following is a list of flags along with the conditions under which they are valid: •...
Page 704 Interrupts Writes posted together at the beginning of the same second take effect together at the next 1 Hz tick. The following sequence is safe and does not result in any spurious interrupts from a previous state. 1. Wait for 1 Hz tick. 2.
Page 705 19 WATCHDOG TIMER – ADSP-2147X The ADSP-2147x processors include a 32-bit watchdog timer (WDT) that can be used to implement a software watchdog function. The timer can improve system reliability by forcing the processor to a known state through generation of a system reset if the timer expires before being reloaded by software.
Page 706 Features Table 19-1. Watchdog Timer Specifications (Cont’d) Feature Availability DMA Channels DMA Chaining Interrupt Source Boot Capable Local Memory Clock Operation WDTCLKIN Features The following list provides a brief description of the watchdog timer’s features. • Programmable time out period – with about 1 second with 12 MHz clock.
Page 707 WatchDog Timer – ADSP-2147x • Programmable trip counter which allows programs to set the num- ber of times the WDT can expire before the signal is WDTRSTO asserted continuously. • WDT space is locked and can be accessed only after unlocking the space using commands.
Page 708 Clocking Trip Register (WDTTRIP). Sets the number of times that the WDT can expire before the pin is continually asserted until the next time WDTRSTO hardware reset is applied. Unlock Register (WDTUNLOCK). Protects the WDT configuration space (WDTCTL, WDTCNT, WDTCURCNT and WDTTRIP regis- ters) against accidental writes from the processor core.
Page 709 WatchDog Timer – ADSP-2147x it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would nor- mally reload the timer, has stopped running due to an external event or software error.
Page 710 Operating Mode DM, PM BUS WDT REGISTERS INTERFACE PCLK/WDTCLK SYNC CHIP RESET COUNTER AND WDT RESET RESET LOGIC WDT_RSTO PCLK/WDTCLK SYNC WATCH DOG TIMER WDTCLK WDTCLKSEL CLOCK GENERATOR (Resonator/Oscillator) WDT_CLKIN WDT_CLKO Figure 19-1. Watchdog Timer Block Diagram Operating Mode The WDT operates in trip count mode as described below. Trip Count The WDT contains a software programmable trip counter register that sets the number of times that the timer can expire before the...
Page 711 WatchDog Timer – ADSP-2147x Debug Features The following section provides information on debugging features avail- able with the watchdog timer. Emulation Considerations An emulation halt stops the WDT counter. The WDT resumes counting after being released from emulation halt. Single stepping is not supported for WDT in emulation mode.
Page 712 Programming Model period value into the 32-bit register before the watchdog is WDTCNT enabled. Once the watchdog is started, the period value cannot be altered. To start the watchdog timer: 1. Unlock the WDT configuration registers by writing the unlock “command”...
Page 713 WatchDog Timer – ADSP-2147x written are ignored, but the write command cause the WDTCURCNT register to be reloaded from the register. If the watchdog is WDTCNT enabled with a zero value loaded to the counter, WDT expires immediately and resets the system. The bit of the watchdog WDRO control register is also set.
Page 714 Programming Model 19-10 ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 715 20 UART PORT CONTROLLER The universal asynchronous receiver/transmitter (UART) is a full-duplex peripheral compatible with the PC-style, industry-standard UART. The interface specifications are shown in Table 20-1. Table 20-1. UART Specifications Feature Availability Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control...
Page 716 Features Table 20-1. UART Specifications (Cont’d) Feature Availability DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation PCLK Features The UART converts data between serial and parallel formats. The serial format follows an asynchronous protocol that supports various word lengths, stop bits, and parity generation options.
Page 717 UART Port Controller SRU Programming The SRU (signal routing unit) needs to be programmed in order to con- nect the UART signals to the output pins or connect the output of the transmitter to the receiver. The UART signals need to be routed as shown Table 20-2.
Page 718 Clocking Transmit Buffer Control Register (UARTxTXCTL). Controls core or DMA operation. Receive Buffer Control Register (UARTxRXCTL). Controls core or DMA operation. Interrupt Enable Control Register (UARTxIER). Enables interrupt requests from system handling. Line Status Register (UARTxLSR). Returns status of controls format of the data character frames as overrun or framing errors and break interrupts.
Page 719 UART Port Controller  The 16-bit divisor formed by the registers UARTDLH UARTDLL resets to 0x0001, resulting in the highest possible clock frequency by default. If the UART is not used, disabling the UART clock saves power (see bits 13 and 14 in the “System and Power Manage- ment Registers”...
Page 720 Functional Description the RS-485 data interface standard. The UART has its own set of control and status registers (Figure 20-1). UARTx_RX_I MASTER LINE CONTROL/ RX CONTROL STATUS BAUD UART DMA DIVISOR GENERATOR ARBITER/DATA MUX LATCH LINE CONTROL/ TX CONTROL STATUS CORE INTERFACE MASTER IOD0...
Page 721 UART Port Controller Serial Communication The UART follows an asynchronous serial communication protocol with these options: • 5 – 8 data bits • 1 or 2 stop bits • None, even, or odd parity • Baud rate = PCLK/(16 × divisor), divisor value can be from 1 to 65,536 All data words require a start bit and at least one stop bit.
Page 722 Operating Modes Operating Modes The two UART operation modes are described in the following sections. Data Packing The UART provides packed and unpacked modes of data transfer to and from the internal memory of the processors. This mode is set using the bit (bit 0) in the register.
Page 723 UART Port Controller transmitter transmits the bit instead of the parity bit. During 9-bit TX9D transmission mode, the parity select controls and the word length select do not have any effect. For the receiver, set the bit in the register and the UART_MODE UAEN in the...
Page 724 Data Transfer Types latter clears the bit. Reading the register clears both the UARTRBR address-detect and the data-ready interrupts. In non-packed mode, when the address-detect interrupt is generated, it means that the data is ready in the RBR buffer while in packed mode, this is not the case.
Page 725 UART Port Controller ) initiates the transmit operation and reads from this address UARTTHR return the register. UARTRBR Note that data is transmitted and received by the least significant bit (LSB) first (bit 0) followed by the most significant bits (MSBs). 31 30 29 28 27 26 25 24 23 22...
Page 726 Data Transfer Types 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Zero-Filled Higher Byte (23–16) RX9D1 11 10 Zero-Filled Lower Byte (7–0) RX9D0 Figure 20-4. UART Receive Buffer Register length of a single word. A receive filter removes spurious pulses of less than two times the sampling clock period.
Page 727 UART Port Controller register. Reading the register when it is not full returns the previ- UARTRBR ously received value. When the register is not read in time, newly UARTRBR received data overwrites the register and the overrun ( ) flag UARTRBR UARTOE is set.
Page 728 Interrupts registers) and enabling DMA using the bits. A DMA UARTRXCTL UARTDEN can be interrupted by resetting the bit in the control register. A UARTDEN DMA request that is already in the pipeline completes normally. DMA Chaining DMA chaining is enabled by setting the bit in the transmit and UARTCHEN receive control registers.
Page 729 UART Port Controller Table 20-4. UART Interrupt Overview Interrupt Interrupt Condition Interrupt Interrupt Default IVT Source Completion Acknowledge DPI UART – DMA RX/TX done Internal transfer For UART DMA: P14I (TX/RX) – Core RX buffer full completion Read to clear –...
Page 730 Interrupts Listing 20-1. Enabling DPI UART Interrupts bit set mode1 IRPTEN; /* enables global interrupts */ bit set imask P1I; /* unmasks P1I interrupt */ ustat1=dm(PICR0); /* route UART0_RXI 0x13 to P1I */ bit set ustat1 P1I4|P1I1|P1I0; bit clr ustat1 P1I3|P1I2; dm(PICR0)=ustat1;...
Page 731 UART Port Controller For DMA, the transmit interrupt is generated when a DMA in transmit mode is complete whereas the receive interrupt is generated when a receive DMA is complete or when a receive error occurs. The register UARTRXSTAT reports whether the interrupt is due to DMA completion or errors. For information on using the UART for DMA transfers, see “DMA Transfers”...
Page 732 Interrupts When initiating the transmission of a string, no special handling of the first character is required. Set the bit (bit 1) and let the inter- UARTTBEIE rupt service routine (ISR) load the first character from memory and write it to the register in the normal manner.
Page 733 UART Port Controller Error Interrupts bit (bit 2 of the register) enables interrupt genera- UARTLSIE UARTIER tion on an independent interrupt channel when any of the following conditions are raised by the respective bit in the UART line status register UARTLSR •...
Page 734 Debug Features Debug Features The following sections describe the debugging features available on the UART. Shadow Registers Because of the destructive nature of reading the following registers: inter- rupt identification ( ), line status ( ) and read buffer UARTIIR UARTLSR ) shadow registers are provided for reading the contents of the UARTRBR...
Page 735 UART Port Controller Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference. UART Effect Latency After the UART registers are configured the effect latency is 2 cycles. PCLK Note that when transmitting data the effective data on DPI pins can’t be seen immediately after 2 cycles because the time which the UART PCLK...
Page 736 Programming Model 3. Send test data through the host device that can be used for calculat- ing the baud rate of the incoming signal. A NULL character (0x00) can be used for this purpose. 4. The baud rate can be derived from the width of timer as follows: BAUDR = Width ÷...
Page 737 UART Port Controller 3. Set up the appropriate control register to enable the UART trans- mitter and receiver, chain pointer, and DMA ( UARTDEN bits). Once chain pointer DMA is enabled, the UARTEN UARTCHEN DMA engine fetches the index, modify, count, and chain pointer values from the memory address specified in the chain pointer reg- ister.
Page 738 Programming Model Programming Model for Core Transfers The following is the general procedure for transferring data using the core. 1. Clear the registers to zero. UARTTXCTL UARTRXCTL 2. Configure the UARTLCR UARTDLL UARTDLH UARTSCR registers. UARTMODE 3. Program the registers to generate interrupt when the trans- UARTIER mit buffer is empty and / or the receive buffer is full.
Page 739 21 TWO WIRE INTERFACE CONTROLLER The two wire interface (TWI) controller allows a device to interface to an inter-IC bus as specified by Philips. The TWI is fully compatible with the widely used I C bus standard. It is designed with a high level of function- ality and is compatible with multi-master, multi-slave bus configurations.
Page 740 Features Table 21-1. TWI Specifications (Cont’d) Feature Availability Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation PCLK Features The TWI is fully compatible with the widely used I C bus standard.
Page 741 Two Wire Interface Controller • Master clock synchronization and support for clock low extension • Separate multiple-byte receive and transmit FIFOs • Low interrupt rate • Individual override control of data and clock lines in the event of a bus lockup •...
Page 742 SRU Programming SRU Programming The TWI signals are available through the SRU2, and are routed as described in Table 21-3. Table 21-3. TWI DPI/SRU2 Signal Connections Internal Node DPI Group SRU2 Register Inputs TWI_CLK_I Group A SRU2_INPUT0 TWI_DATA_I Outputs TWI_CLK_PBEN_O Group C TWI_DATA_PBEN_O Clocking...
Page 743 Two Wire Interface Controller Register Overview This section provides brief descriptions of the major registers. For com- plete information see “Two Wire Interface Registers” on page A-253. Slave Mode Control Register (TWISCTL). Controls the logic associated with slave mode operation. Settings in this register do not affect master mode operation and should not be modified to control master mode functionality.
Page 744 Functional Description FIFO Control Register (TWIFIFOCTL). The FIFO control register affects only the FIFO and is not tied in any way with master or slave mode operation. FIFO Status Register (TWIFIFOSTAT). The fields in the TWI FIFO sta- tus register indicate the state of the FIFO buffers’ receive and transmit contents.
Page 745 Two Wire Interface Controller TWI_DATA_PBEN_O (OPEN DRAIN) TRANSMIT SHIFT REGISTER FIFO ARBITRATION RECEIVE SHIFT REGISTER TWI_DATA_I (OPEN DRAIN) CORE BUS INTERFACE ADDRESS COMPARE PCLK PRESCALER REGISTERS TWI_CLK_PBEN_O CLOCK GENERATION TWI_CLK_I Figure 21-1. TWI Block Diagram The address compare block supports address comparison in the event the TWI controller module is accessed as a slave.
Page 746 Functional Description The TWI controller’s clock output follows these rules: • Once the clock high ( ) count is complete, the serial clock out- CLKHI put is driven low and the clock low ( ) count begins. CLKLOW • Once the clock low count is complete, the serial clock line is three-stated and the clock synchronization logic enters into a delay mode (shaded area) until the line is detected at a logic 1...
Page 747 Two Wire Interface Controller 7-BIT ADDRESS 8-BIT DATA S = START P = STOP ACK = ACKNOWLEDGE Figure 21-3. Standard Data Transfer To better understand the mapping of TWI controller register contents to a basic transfer, Figure 21-4 details the same transfer as above noting the corresponding TWI controller bit names.
Page 748 Functional Description TWI_CLOCK (BUS) TWI CONTROLLER DATA SECOND MASTER DATA TWI_DATA (BUS) ARBITRATION LOST START Figure 21-5. TWI Bus Arbitration Start and Stop Conditions Start and stop conditions involve serial data transitions while the serial clock is at logic 1 level. The TWI controller generates and recognizes these transitions.
Page 749 Two Wire Interface Controller The TWI controller’s special-case start and stop conditions include: • TWI controller addressed as a slave-receiver If the master asserts a stop condition during the data phase of a transfer, the TWI controller concludes the transfer ( TWISCOMP •...
Page 750 Data Transfer Data Transfer The TWI uses its transmit and receive buffers for data transfer (no DMA capability). These buffers are described in the following sections. Data Buffers The TWI has two data buffer FIFOs, which are described in the following sections.
Page 751 Two Wire Interface Controller rates and peripheral bus access times, a double byte transfer data access can be performed. Two data bytes can be written, effectively filling the trans- mit FIFO buffer with a single access. The data is written in little-endian byte order where byte 0 is the first byte to be transferred and byte 1 is the second byte to be transferred.
Page 752 Operating Modes 16-Bit Receive FIFO Register The TWI 16- bit FIFO receive register ( ) shown in Figure 21-10 RXTWI16 holds a 16-bit data value read from the FIFO buffer. Although peripheral bus reads are 32 bits, a read access to the register can only access RXTWI16 two receive data bytes from the FIFO buffer.
Page 753 Two Wire Interface Controller troller is a slave-receiver. If the data associated with the transfer is to be not acknowledged (NAKed), the bit can be set. TWINAK If the TWI controller is to issue a general call as a master-transmitter, the appropriate address and transfer direction can be set along with loading transmit FIFO data.
Page 754 Interrupts Table 21-4. TWI Interrupt Overview Interrupt Interrupt Condition Interrupt Interrupt Default IVT Source Completion Acknowledge DPI TWI – Master (TX completion, TX/RX Internal transfer W1C (Write one P14I (TX/RX) buffer service, error) completion to clear) TWI- – slave (initiative, completion, IRPTL register + overflow, error) RTI instruction...
Page 755 Two Wire Interface Controller rupts. (By default, these interrupts are not configured in the IRPTL register—the register has to be programmed to configure them.) PICRx This method shown in Listing 21-2 uses the register with the code PICR value of the interrupts.
Page 756 Debug Features registers must also be configured based on the program- IMASK LIRPTL mable interrupt to be used. The ISR needs to clear the status bits of the register by explicitly writing 1 into the status bit (W1C) as TWIIRPTL shown in Listing 21-3.
Page 757 Two Wire Interface Controller Effect Latency The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific). Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference.
Page 758 Programming Model Slave Mode When enabled, slave mode supports both receive and transmit data trans- fers. It is not possible to enable only one data transfer direction and not acknowledge (NAK) the other. This is reflected in the following setup. 1.
Page 759 Two Wire Interface Controller Table 21-5. Slave Mode Setup Interaction (Slave Addressed as Receiver) TWI Controller Master Processor Interrupt: TWISINIT – Slave transfer has been Change on the next sides always. initiated. Interrupt Acknowledge: W1C the TWIIRPTL register. Interrupt: TWIRXS – Receive buffer has 1 or 2 Read receive FIFO buffer.
Page 760 Programming Model 3. Program the register. Indicate if transmit FIFO buffer TWIFIFOCTL interrupts should occur with each byte transmitted (8 bits) or with each 2 bytes transmitted (16 bits). 4. Program the register. Enable the bits associated with the TWIIMASK desired interrupt sources.
Page 761 Two Wire Interface Controller 2. Program the register. Indicate if receive FIFO buffer TWIFIFOCTL interrupts should occur with each byte received (8 bits) or with each 2 bytes received (16 bits). 3. Program the register. Enable bits associated with the TWIIMASK desired interrupt sources.
Page 762 Programming Model Repeated Start Condition In general, a repeated start condition is the absence of a stop condition between two transfers initiated by the same master. The two transfers can be of any direction type. Examples include a transmit followed by a receive, or a receive followed by a transmit.
Page 763 Two Wire Interface Controller • Set the bit (or earlier when register is pro- RSTART TWIMCTL grammed first). • Set the bit to indicate the next transfer direction is TWIMDIR receive. This should be done before the addressing phase of the next transfer begins.
Page 764 Electrical Specifications The tasks performed at each interrupt are: • interrupt TWIRXINT This interrupt is generated due to the arrival of one or two data bytes into the receive FIFO. The bit should be set at this TWIRSTART time (or earlier) and should be cleared to reflect the change in MDIR direction of the next transfer.
Page 765 22 POWER MANAGEMENT Power management is a vital tool that system designers can employ to control internal and external clocking and maximize power savings. Features The following list describes the power management features. • The PLL has various multiplier and divisor settings to generate a flexible core clock.
Page 766 Phase-Locked Loop (PLL) Phase-Locked Loop (PLL) The following sections describe the clocking system of the SHARC pro- cessor. This information is critical to ensure designs that work correctly and efficiently. Functional Description To provide the clock generation for the core and system, the processor uses an analog PLL with programmable state machine control.
Page 767 Power Management multiplication range, the processor uses a combination of programmable multipliers in the PLL feedback circuit and output configuration blocks. The processor uses an on-chip, phase-locked loop (PLL) to generate its internal clock, which is a multiple of the frequency.
Page 768 Phase-Locked Loop (PLL) PLL Multiplier The PLL multiplier is controlled by hardware or software and based on the PLL multiplier settings below. • Hardware—through the clock configuration pins ( CLK_CFG1–0 • Software—the hardware settings are overridden through the PLLM bits PLLM Hardware Control On power-up, the pins are used to select core to...
Page 769 Power Management PLL VCO The VCO is the PLL output stage of the PLL. It feeds the output clock generator which provides core and peripheral clocks as shown in Table 22-1. Two settings have an impact on the VCO frequency: •...
Page 770 Phase-Locked Loop (PLL) If the bit is set, new post divider ratios are picked up on the fly and DIVEN the clocks smoothly transition to their new values within 14 core clock ) cycles. CCLK  Post divider ratio changes ( bits) do not require bypass mode.
Page 771 Power Management phase-locked loop. Note that the goal in selecting a particular clock ratio for an application is to provide the highest permissible internal frequency for a given frequency. For more information on available clock CLKIN rates, see the appropriate product data sheet. Table 22-2.
Page 772 Power-Up Sequence Normal Mode The normal mode is the regular mode and is effective if the bit is PLLBP cleared. In normal mode the PLL has locked and multiplies to the CLKIN desired VCO clock. The output clock generator post divides and provides the clock tree to the I/O.
Page 773 Power Management PLL Start-Up Before the PLL can start settling, the signal should be asserted for RESET several micro-seconds under the following conditions. For PLL informa- tion, see the appropriate product data sheet. • Valid and stable core voltage ( VDDINT •...
Page 774 Power Management  The advantage of the delayed core reset is that the PLL can be reset any number of times without having to power down the system. If there is a brownout situation, the external watchdog circuit only has to control the signal.
Page 775 Power Management External Port Control bit in the register allows programs to disconnect the EPOFF PMCTL1 clocks to the SDRAM and AMI modules in order to save power if the con- trollers are not used. Note that if the SDRAM/DDR2 controller is used but pauses, the self-refresh mode also helps to reduce power consumption.
Page 776 Power Management Disconnect DAI/DPI Pin Buffers If a DAI/DPI pin is not being used, its pin enable (for example ) and its input ( ) for its pin buffer should be con- DAI_PBENxx_I DAI_PBxx_I nected to low. Disable the S/PDIF Reciever Disable the S/PDIF receiver and its digital PLL from the S/PDIF receiver.
Page 777 Power Management General Notes on Power Savings The following are some additional methods for reducing power. • The lower the operation frequency, the lower the power consump- tion. The core and peripherals should be operated at the lowest frequency that meets the system’s requirements. Active power is proportional to the processor’s core clock frequency.
Page 778 Programming Models Post Divider Use the following procedure and the example shown in Listing 22-2 program or reconfigure the divider. 1. Disable any peripheral (configured with /2). Note that PCLK CCLK the peripherals cannot be enabled when changing VCO to core clock ratio.
Page 779 Power Management Multiplier and Post Divider Programming Model There are two allowable procedures to program the VCO. The first method is shown in Listing 22-3. 1. Set the PLL multiplier and divisor value and enable the divisor by setting the bit.
Page 780 Programming Models Listing 22-3. VCO Programming: First Method ustat2 = dm(PMCTL); bit clr ustat2 PLLM63|PLLD16; /* Clear the old multiplier and divider values */ bit set ustat2 DIVEN | PLLD4 |PLLM16; /* set a multiplier of 16 and a divider of 4 */ dm(PMCTL) = ustat2;...
Page 781 Power Management bit set ustat2 PLLBP | PLLD4 |PLLM16; /* set a multiplier of 16 and a divider of 4 */ dm(PMCTL) = ustat2; waiting_loop: r0 = 4096; /* wait for PLL to lock at new rate (requirement for VCO change) */ lcntr = r0, do pllwait until lce;...
Page 782 Programming Models Listing 22-5. Back to Back Bypass ustat3 = dm(PMCTL); bit clr ustat3 PLLBP; dm(PMCTL) = ustat3; /* PLLBP is cleared */ nop;nop;nop;nop; ustat4 = dm(PMCTL); bit set ustat4 PLLBP; dm(PMCTL) = ustat4; /* PLLBP is set */ 22-18 ADSP-214xx SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 783 23 SYSTEM DESIGN This chapter discusses different processor reset methods, boot modes and pin multiplexing. In addition, information about high speed design is illustrated with some examples of supervisor circuits used in conjunction with the SHARC processor. These topics are located in the following sections.
Page 784 Pin Descriptions • Two pin multiplexing groups: core flag pins and external port pins. • DAI/DPI units work together with multiplexing logic provides sys- tem design flexibility. Pin Descriptions Refer to the appropriate product data sheet for pin information, including package pinouts for the currently available package options.
Page 785 System Design SPI DMA Control Register (SPIDMAC). Configures the SPI as receive DMA which generates an interrupt during boot. SPI Slave Select Control Register (SPIFLGx). Controls the slave select configuration for SPI as master during SPI boot. SPI Baudrate Register (SPIBAUD). Controls the frequency for SPICLK master mode during boot.
Page 786 Processor Reset Table 23-1. Reset Function Overview (Cont’d) Reset Function Hardware Reset Software Reset Running Reset Core Internal Memory Peripherals Yes (except SDRAM/DDR2) Booting Power Management Emulation Unit 1 Internal memory array does not have reset. Only power up/down can change array contents, (or direct read/write by the core or DMA).
Page 787 System Design • The processor core and peripherals are reset exactly as if a Power-on (hardware) reset is asserted, except: • The SDRAM/DDR2 controllers continue to run and refresh as programmed. • The contents of external SDRAM/DDR2 are unaffected, and retain their values prior to a running reset. •...
Page 788 Processor Reset System Considerations It is important that an external 10 kΩ pull-up resistor is placed on the pin if it is intended to be used as an input for initiating a run- RESETOUT ning reset as shown in Figure 23-1.
Page 789 System Design There are several possible methods that can be used to implement running reset. The following illustrates one example of a running reset implemen- tation involving an SHARC processor and a host processor. External Host In an AVR (audio-video receiver) system, a host microcontroller may communicate with the processor using the serial peripheral interface (SPI) or, if no SPI pins are available on the host device, it can use spare flag I/Os to connect with the SPI of a SHARC as shown in...
Page 790 Processor Booting Boot Mechanisms In order to ensure proper device booting, the following hardware mecha- nisms are available on the processor. • Peripheral boot configuration pins ( ) configure which BOOT_CFGx peripheral boot stream is activated after power-up. • Peripheral control and DMA parameter settings define the DMA channel which is started after is asserted based on the RESETOUT...
Page 791 System Design  pin is disabled during external port booting. The received data streams of 4x8-bit data words are packed by the AMIRX buffer into 32-bit words least significant bit (LSB) first, and passed through the DMA’s 6 deep external port buffer into the internal DFEP0 memory...
Page 792 Processor Booting Table 23-2. AMICTL1 Boot Settings (0x5C1) (Cont’d) Name Setting ACKEN ACK pin disabled (cleared = 0) 10–6 23 wait state cycles = 10111 13–11 Bus hold cycle at the end of write access = 000 16–14 No bus idle cycle = 000 FLSH Buffer holds data (cleared = 0) 20–18...
Page 793 System Design Table 23-4. DMAC0 Boot Settings (0x1000001) (Cont’d) Name Setting DLEN No delay line DMA (cleared = 0) CBEN No circular DMA (cleared = 0) DFLSH Disabled (cleared = 0) WRBEN Disabled (cleared = 0) OFCEN Disabled (cleared = 0) TLEN Disabled (cleared = 0) INTIRT...
Page 794 Processor Booting SPI Port Booting The SHARC processors support booting from a host processor using SPI slave mode or booting from an SPI flash, SPI PROM, or a host processor via SPI master mode. Both SPI boot modes (master and slave) support 8-, 16-, or 32-bit SPI devices.
Page 795 System Design Table 23-6. SPIDMAC Master/Slave Boot Settings (0x7) (Cont’d) Setting Comment FIFOFLSH Cleared (= 0) FIFO flush INTERR Cleared (= 0) SPI DMA error interrupts Table 23-7. SPICTL Master Boot Settings (0x5D06) Setting Comment SPIEN Set (= 1) SPI enabled SPIMS Set (= 1) Master device...
Page 796 Processor Booting Master Header Information The transfer is initiated by the transferring the necessary header informa- tion on the interface (consisting of the read opcode and the starting address of the block to be transferred, which is usually all zeros). The read opcode is fixed as 0xC0 (LSBF format) and is 24-bits long.
Page 797 System Design SPI_FLG0_O SPI_CLK_O 16-BIT ADDRESS 8-BIT INSTRUCTION SPI_MOSI_O WORD VALID EPROM BITS SPI_MISO_i Figure 23-4. SPI Master Mode Booting Using Various Serial Devices Slave Boot Mode In slave boot mode, the host processor initiates the booting operation by activating the signal and asserting the signal to the active SPICLK...
Page 798 Processor Booting Since the SPI host initiates the transfers, a handshake between master and slave is required for synchronization. One possible solution is to use the slave’s signal as handshake signal. If a pause is required, the SPI_MISO_O slave transmits zeros or ones to the master. Another solution is to connect this signal to the master’s flag input to generate an interrupt for the same purpose.
Page 799 System Design SPI Boot Packing In all SPI boot modes, the data word size in the shift register is hardwired to 32 bits. Therefore, for 8- or 16-bit devices, data words are packed into the shift register to generate 32-bit words least significant bit (LSB) first, which are then shifted into internal memory.
Page 800 Processor Booting Figure 23-5 shows how a pair of instructions are packed for SPI booting using a 32-, 16-, and an 8-bit device. These two instructions are received as three 32-bit words. The following sections examine how data is packed into internal memory during SPI booting for SPI devices with widths of 32, 16, or 8 bits.
Page 801 System Design 16-Bit SPI Packing Figure 23-7 shows how a 16-bit SPI host packs 48-bit instructions at PM addresses PMaddr0 and PMaddr1. For 16-bit hosts, two 16-bit words are packed into the shift register to generate a 32-bit word. The 32-bit word shifts to internal program memory during the kernel load.
Page 802 Processor Booting 8-Bit SPI Packing Figure 23-8 shows how an 8-bit SPI host packs 48-bit instructions exe- cuted at PM addresses PMaddr0 and PMaddr1. For 8-bit hosts, four 8-bit words pack into the shift register to generate a 32-bit word. The 32-bit word shifts to internal program memory during the load of the 256-instruction word kernel.
Page 803 System Design to 384 words. Since one 32-bit word is created from four packed 8-bit words, the total number of 8-bit words transmitted is 1536. Link Port Booting Booting is supported through link port 0. The values for BOOT_CFG2–0 selecting link port boot is 100. The booting procedure is the same as any other boot mode.
Page 804 Processor Booting Table 23-11 shows the link port control settings after reset. Table 23-11. LPCTL0 Boot Settings (0x403) Name Setting Link port enabled (set = 1) LDEN DMA enabled (set = 1) LCHEN DMA Chaining (cleared = 0) LTRAN Receive operation (cleared = 0) Buffer hang disabled (cleared = 0) LTRQ_MSK LP transmit request mask (cleared = 0)
Page 805 System Design Kernel Boot Time This section illustrates the minimum required booting time for the kernels (provided by the tools). There are five timing windows which describe together the entire boot process shown in the list below and Table 23-13. (core is in reset) RESET RESETOUT...
Page 806 Programming Model ROM Booting There are two access types (modes) available for ROM booting: secured and non secured modes which are described below. Secured ROM (hardware security switch = 1. In this mode: • pins are ignored. BOOTCFG2-0 • Emulation is enabled only when the user enters a valid key. •...
Page 807 System Design Running Reset Using the SPI protocol with additional control words and commands, running reset can become an addition command from the host or from the processor as described in the following procedure. 1. The host initiates a running reset by informing the processor over the command interface.
Page 808 Programming Model Executing the Boot Kernel 1. The DMA completes (counter zero) and the interrupt associated with the peripheral that the processor is booting from is activated. 2. The processor jumps to the applicable interrupt vector location and executes the RTI instruction located there (only). ...
Page 809 System Design This overrides the kernel with the application’s IVT. However, the application needs to temporarily include the RTI instruction at the peripheral interrupt address, allowing a return from interrupt. Moreover, the last instruction in the final routine is a jump (db) including an IDLE.
Page 810 Pin Multiplexing During the boot process, word packing (for example 8 to 32-bit) is per- formed over the SPI. In other words, the kernel is not loaded directly with 256 x 48-bit words, instead it is loaded with 384 x 32-bit ‘packed words’ (2-column access).
Page 811 System Design  Flag pins ( ) are connected as input after reset. FLG3-0 If more than four flags are required, they can multiplexed using the exter- nal port pins in the register or the DPI pins in the DPI registers. SYSCTL For a detailed flag description refer to the SHARC Processor Programming Reference.
Page 812 Pin Multiplexing • FLAGs (I/O) • PWM channels (output) Multiplexed External Port Pins The external port address and data pins are used to multiplex the external port interface with other peripherals. Table 23-15 provides the pin settings. Table 23-15. EPDATA Truth Table (SYSCTL Register) EPDATA ADDR31–16 ADDR15–8...
Page 813 System Design Backward Compatibility The multiplexing scheme is not backward compatible to previous SHARC processors. On previous SHARC processors only the external port data pins are multiplexed. With the ADSP-214xx processors, address and data pins of the external port are multiplexed. Parallel Connection of Flag Pins via External Port and DPI Pins The various external port multiplexing (shown in...
Page 814 Pin Multiplexing FLAG0 FLAG0_PIN IRQ0 FLAG1 FLAG1_PIN PWM15-4 (ADSP-2147X, IRQ1 ADSP-2148X) PINS FLAGS15-4 FLAG2 IRQ2 FLAG2_PIN FLAGS3-0 PWM3-0 FLAG3 FLAG3_PIN FLAGS7-4 TMREXP PWM7-4 MULTIPLEXING IN GROUPS OF 4 ONLY FLAGS11-8 PWM11-8 ADDR23-8 11-8 PDAP_DATA19-4 FLAGS/PWM15-0 FLAGS15-12 PWM15-12 ADDR7-0 15-12 PDAP_DATA/CTRL FLAGS15-8 DATA7-0 SOLID LINES INDICATE DEFAULT...
Page 815 System Design High Frequency Design Because the processor must be able to operate at very high clock frequen- cies, signal integrity and noise problems must be considered for circuit board design and layout. The following sections discuss these topics and suggest various techniques to use when designing and debugging target systems.
Page 816 High Frequency Design RESETOUT Circuit boards should have a test pad for the pin This pin can be RESETOUT used as handshake signal for booting or as clock out ( frequency) for CLKIN a debug aid to verify the processor is active and running. Input Pin Hysteresis Hysteresis (shown in Figure...
Page 817 GPIO inputs that are edge-sensitive be driven from sources that have series termination resistors. The values for the series resistor can be determined by simulating with the IBIS models. These models can be found on the Analog Devices web site. ADSP-214xx SHARC Processor Hardware Reference 23-35...
Page 818 High Frequency Design Asynchronous Inputs The processor has several asynchronous inputs such as IRQ2-0 FLAG3–0 and the DAI/DPI pins and reset inputs , running reset RESET TRST which can be asserted in arbitrary phase to the reference clocks. The pro- cessor synchronizes the reset inputs to the input while the CLKIN...
Page 819 System Design Circuit Board Layout This section gives recommendations to physical layouts for high speed designs. • Place the oscillator close to the destination. • Place the series termination close to the clock source. For trace routing: • Place a GND plane below the oscillator and buffer. •...
Page 820 High Frequency Design • To allow better control of impedance and delay, and to reduce crosstalk, design for lower transmission line impedances. • Experiment with the board and isolate crosstalk and noise issues from reflection issues. This can be done by driving a signal wire from a pulse generator and studying the reflections while other components and signals are passive.
Page 821 System Design EZ-KIT Lite Schematics The EZ-KIT Lite® evaluation system schematics are a good starting refer- ence. Because the EZ-KIT Lite board is for evaluation and development, extra circuitry is provided in some cases. Read the EZ-KIT Lite board schematic carefully, because sometimes a component is not populated and sometimes it has been added to make it easier to access.
Page 822 System Components • Transmission Lines • Ground Planes and Layer Stacking • Terminations • Vias • Power Systems • Connectors • Ribbon Cables • Clock Distribution • Clock Oscillators High-Speed Digital Design: A Handbook of Black Magic, Johnson & Gra- ham, Prentice Hall, Inc., ISBN 0-13-395724-1.
Page 823 The signal should not only offer a suitable RESET delay, but it should also have a clean monotonic edge. Analog Devices has a range of microprocessor supervisory ICs with different features. Features include one or more of the following.
Page 824 System Components A simple power-up reset circuit is shown in Figure 23-13 using the ADM809-RART reset generator. The ADM809 provides an active low signal whenever the supply voltage is below 2.63 V. At power-up, a RESET 240 ms active reset delay is generated to give the power supplies and oscil- lators time to stabilize.
Page 825 System Design V DDEXT 10μF V SENSE 100nF V DDEXT 100nF ADM706TAR RESET ADSP-214xx IRQ0 Vt=+1.25V IRQ1 FLAG0 RESET Figure 23-14. Reset Generator and Power Supply Monitor Definition of Terms Booting When a processor is initially powered up, its internal SRAM and many other registers are undefined.
Page 826 Definition of Terms These kernel files (DXE, ASM) are supplied with the VisualDSP++ devel- opment tools for all boot modes. For more information on the kernels, refer to the tools documentation Boot Master/Slave How a processor boots is dependent on the peripheral used. See “Proces- sor Booting”...
Page 827 For convenience and consistency, Analog Devices supplies a header file that provides these bit ADSP-214xx SHARC Processor Hardware Reference...
Page 828 Overview and registers definitions. An #include file is provided with VisualDSP++ tools and can be found in the directory. VisualDSP/214xx/include Overview The I/O processor’s registers are accessible as part of the processor’s mem- ory map. “Register Listing” on page A-273 lists the I/O processor’s memory-mapped registers and provides a brief description of each register.
Page 829 Registers Reference • The bit descriptions in the figures are intentionally brief, contain- ing only the bit mnemonic, location, and function. More detailed information can be found in the tables that follow the register drawings and in the chapters that describe the particular module. •...
Page 830 System and Power Management Registers Table A-1. Bit Type Usage (Cont’d) Bit Type Description Usage Write-Only WO bits are used primarily in control/status register to trigger events like self-refresh or power-up sequence for SDRAM. Note that these bit type always read zero Write-Only-to-Clear WOC bits are used primarily in control/status regis- ter to flush data FIFOs and to clear its status bits.
Page 831 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IRQ0EN PWMONDPIEN Flag0 Mode DPI Pins as PWM Signals IRQ1EN PWM3EN Flag1 Mode Pulse Width Modulation Select IRQ2EN PWM2EN Flag2 Mode Pulse Width Modulation Select TMREXPEN PWM1EN Flag3 Mode...
Page 832 System and Power Management Registers Table A-2. SYSCTL Register Bit Descriptions (Cont’d) Name Description 23–21 EPDATA AMI Mode Select. Selects between multiplexed AMI, Flags, PWM and PDAP interfaces on the AMI bus. For detailed programming modes for these bits, see “Multiplexed External Port Pins”...
Page 833 Registers Reference Power Management Control Registers (PMCTL) The following sections describe the registers associated with the processors power management functions. The power management control register, shown in Figure A-2, is a 32-bit memory-mapped register. This register contains bits to control phase lock loop (PLL) multiplier and divider (both input and output) values, PLL bypass mode, and clock enabling control for peripherals (see Table A-3 on...
Page 834 System and Power Management Registers Table A-3. PMCTL Register Bit Descriptions (RW) Name Description 5–0 PLLM PLL Multiplier. PLLM = 0 PLL multiplier = 128 × 0<PLLM<63 PLL multiplier = 2 PLLM Reset value = CLK_CFG1–0 00 = 000110 = 6x 01 = 100000 = 32x 10 = 010000 = 16x 11 = 000110 = 6x (Reserved)
Page 835 Registers Reference Table A-3. PMCTL Register Bit Descriptions (RW) (Cont’d) Name Description 17–16 (RO) CRAT PLL Configuration Ratio, CLK_CFG1-0 pins. After reset, both CLK_CFG pins define the CLKIN to core clock ratio. This ratio can be changed with the PLLM and PLLD bits. CRAT =CLK_CFG[1:0] 0 = CLK_CFG[1:0] = 00 (6:1 ratio) 1 = CLK_CFG[1:0] = 01 (32:1 ratio)
Page 836 System and Power Management Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MLBOFF ACCOFF MLB Clock Shutdown Accelerator Clocks ACCSEL (18–17) Shutdown Accelerator Select 11 10 UART0POFF LP1OFF LP1 Clock Shutdown UART Clock Shutdown LP0OFF TWIOFF...
Page 837 Registers Reference Table A-4. PMCTL1 Register Bit Descriptions (RW) (Cont’d) Name Description DAIOFF Shutdown Clock to DAI. Shutdown clock to DAI related peripherals—SRU, SRC, S/PDIF, PCG, IDP, PDAP 0 = DAI is in normal mode 1 = Shutdown clock to DAI EPOFF Shutdown Clock to External Port.
Page 838 System and Power Management Registers Table A-4. PMCTL1 Register Bit Descriptions (RW) (Cont’d) Name Description ACCOFF Shutdown Clock to Accelerator. 0 = Accelerator is in normal mode 1 = Shutdown clock to accelerator 18–17 ACCSEL Accelerator Select. 00 = Select FIR 01 = Select IIR 10 = Select FFT 11 = Reserved...
Page 839 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRAT (17–16) SDCKR PLL Clock Ratio Core Clock to SDRAM Clock 11 10 PLLBP PLLM (5–0) PLL Multiplier PLL Bypass DIVEN PLLD (7–6) PLL Divider PLL Divider Enable INDIV...
Page 840 System and Power Management Registers Table A-5. PMCTL Register Bit Descriptions (RW) (Cont’d) Name Description 9 (WO) DIVEN Output Clock Divider Enable. This bit enables the post divider settings. 0 = Do not load PLLD 1 = Load PLLD When the PLL is programmed using the multipliers and the post dividers, the DIVEN and PLLBP bits should NOT be programmed in the same core clock cycle.
Page 841 Registers Reference Power Management Control Register 1 (PMCTL1) This register contains the bits for shutting down the clocks to various peripherals and selecting one of the three FIR/IIR/FFT accelerators. The core can write to bits 19–0 of this register.  Writes to this register have an effect latency of two cycles.
Page 842 System and Power Management Registers Table A-6. PMCTL1 Register Bit Descriptions (RW) Name Description UART0OFF Shutdown Clock to UART. 0 = UART is in normal mode 1 = Shutdown clock to UART TWIOFF Shutdown Clock to TWI. 0 = TWI is in normal mode 1 = Shutdown clock to TWI PWMOFF Shutdown Clock to PWM.
Page 843 Registers Reference Table A-6. PMCTL1 Register Bit Descriptions (RW) (Cont’d) Name Description TMROFF Shutdown Clock to Peripheral Timer. 0 = Timer is in normal mode 1 = Shutdown clock to timer Reserved RTCOFF Shutdown Clock to Real-Time Clock. 0 = RTC is in normal mode 1 = Shutdown clock to RTC 15–14 Reserved...
Page 844 ADSP-2146x External Port Registers Running Reset Control Register (RUNRSTCTL) register is used to control the running reset functionality RUNRSTCTL and is described in Table A-7. Table A-7. Running Reset Control Register Bit Descriptions (RW) Name Description PM_RUNRST_PINEN Configures the RESETOUT pin for RUNRST input.
Page 845 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FRZSP (21–19) Arbitration Freezing Length for SPORT DMA 11 10 B0SD FRZCR (14–12) Bank 0 DDR2 DRAM Arbitration Freezing Length for B1SD CORE Accesses Bank 1 DDR2 DRAM FRZDMA (10–8)
Page 846 ADSP-2146x External Port Registers Table A-8. EPCTL Register Bit Descriptions (RW) (Cont’d) Name Description 5–4 EPBR External Port Bus Priority. 00 = Priority order from highest to lowest is SPORT, external port DMA, core 01 = Priority order from highest to lowest is external port DMA, SPORT, core 10 = Highest priority is core.
Page 847 Registers Reference Table A-8. EPCTL Register Bit Descriptions (RW) (Cont’d) Name Description 21–19 FRZSP Arbitration Freezing Length for SPORT DMA. 000 = No Freezing 001 = 4 Accesses 010 = 8 Accesses 011 = 16 Accesses 100 = 32 Accesses 101 = Page size of DDR2 110, 111 = Reserved 31–19...
Page 848 ADSP-2146x External Port Registers Table A-9. AMICTLx Register Bit Descriptions (RW) Name Description AMIEN AMI Enable. 0 = AMI is disabled 1 = AMI is enabled 2–1 Reserved PKDIS Disable Packing/Unpacking. 0 = 8-bit data received packed to 32-bit data. Similarly, 32-bit data to be transmitted is unpacked to four 8-bit data.
Page 849 Registers Reference Table A-9. AMICTLx Register Bit Descriptions (RW) (Cont’d) Name Description 16–14 Bus Idle Cycle. Idle cycle to be inserted whenever read from exter- nal memory is followed by a write to external memory – to avoid contention. 'IC' EP clock cycles are ensured between a read to write.
Page 850 ADSP-2146x External Port Registers Table A-10. AMISTAT Register Bit Descriptions (RO) Name Description AMIMS External Bus Master. 1 = AMI controls the external pins Since the AMI has dedicated pins AMIMS always reads 1. AMIS External Interface Status. 0 = AMI interface idle 1 = AMI access pending 15–4 Reserved...
Page 851 Registers Reference DDR2 Control Register 0 (DDR2CTL0) The DDR register includes the programmable parameters asso- DDR2CTL0 ciated with the DDR configuration. Figure A-9 Table A-11 show the corresponding control bit definitions. The FEMRx FLMR FDLLCAL , and bits are automatically cleared on the SREF_EXIT DDR2SRF DDR2PSS...
Page 852 ADSP-2146x External Port Registers Table A-11. DDR2CTL0 Register Bit Descriptions (RW) Name Description DIS_DDR2CTL Disable DDR2 Controller. Enable or disable the DDR2 con- troller. If the controller is disabled, no accesses to external DDR2 DRAM address spaces occur. All associated control pins (DDR2_RAS, DDR2_CAS, DDR2_WE, DDR2_CS, DDR2_ODT except DDR2_CKE) are in their inactive states and the DDR2 clock is also disabled.
Page 853 Registers Reference Table A-11. DDR2CTL0 Register Bit Descriptions (RW) (Cont’d) Name Description 11–9 DDR2RAW Row Address Width. 000 = 8 bits 001 = 9 bits 111 = 15 bits 12 (WO) FEMR2 Force EMR2 Register Write. Forces EMR2 only if the banks are all precharged.
Page 854 ADSP-2146x External Port Registers Table A-11. DDR2CTL0 Register Bit Descriptions (RW) (Cont’d) Name Description 18 (WO) DDR2SRF Self-Refresh Mode. 0 = No effect 1 = Enters sel-refresh mode DDR2ORF Auto-Refresh Command. If this bit is set, the auto-refresh command is not issue to the DDR2 memory. This mode allows data streaming connection to FPGA were the refresh is not required.
Page 855 Registers Reference Table A-11. DDR2CTL0 Register Bit Descriptions (RW) (Cont’d) Name Description DDR2OPT Read Optimization Enable. 0 = Disable read optimization 1 = Enable read optimization 31–28 DDR2MODIFY Read Modifier (In Optimization Mode). 0000 = Modifier 0 0001 = Modifier 1 …...
Page 856 ADSP-2146x External Port Registers Table A-12. DDR2CTL1 Register Bit Descriptions (RW) Name Description 4–0 DDR2TRAS Row Active Time. 00000 = Reserved 00001 = 1 clock cycle 00010 = 2 clock cycles … 11111 = 31 clock cycles 8–5 DDR2TRP Row Precharge Time. Note that for 8 banked devices the timing spec becomes t + 1t 0000 = Reserved...
Page 857 Registers Reference Table A-12. DDR2CTL1 Register Bit Descriptions (RW) (Cont’d) Name Description 24–22 DDR2TRRD Row to Row Activation Delay. 000 = Reserved. 001 = 1 clock cycle 010 = 2 clock cycles … 111 = 7 clock cycles 29–25 DDR2TFAW Force Activation Window.
Page 858 ADSP-2146x External Port Registers 11 10 DDR2MR (15–14) DDR2BL (2–0) Mode Register Burst Length DDR2DTWR (11–9) DDR2CAS (6–4) Write Recovery Time CAS Latency DDR2DLLRST DLL Reset Figure A-11. DDR2CTL2 Register Table A-13. DDR2CTL2 Register Bit Descriptions (RW) Name Description 2–0 DDR2BL Burst Length.
Page 859 Registers Reference DDR2 Control Register 3 (DDR2CTL3) register includes the programmable parameters associated DDR2CTL3 with the DDR2 extended mode register ( Figure A-12 EMR1 Table A-14 show the DDR2 control register 3 bit definitions. All the val- ues are defined in terms of number of clock cycles. Values written into this register are loaded into the DDR2 extended mode register during power up (or when bit in...
Page 860 ADSP-2146x External Port Registers Table A-14. DDR2CTL3 Register Bit Descriptions (RW) (Cont’d) Name Description 5–3 DDR2AL Additive Latency. Additive latency reduces command bus conflicts to enable commands to be issued more effi- ciently. Note thate the DDR2 controller performance is primary regardless of the AL settings.
Page 861 Registers Reference DDR2 Control Register 4 (DDR2CTL4) register includes the programmable parameters associated DDR2CTL4 with the DDR2 extended mode register 2 ( Table A-15 shows the EMR2 DDR2 control register bit definition. All the values are defined in terms of number of clock cycles.
Page 862 ADSP-2146x External Port Registers  This register’s contents should not be changed while the DDR2 interface is active. Also, whenever this register’s contents are changed an initialization sequence must be executed to reflect this register’s contents in the register. DDR2EMR2 Table A-16.
Page 863 Registers Reference Table A-17. DDR2RRC Register Bit Descriptions (RW) Name Description 13–0 RDIV RDIV value defines the number of clock cycles between two refresh commands. 20–14 Reserved 28–21 Row refresh interval minimum refresh interval in clock cycles. Programmable from 0 to 255. 31–29 Reserved Controller Status Register 0 (DDR2STAT0)
Page 864 ADSP-2146x External Port Registers Table A-18. DDR2STAT0 Register Bit Descriptions (RO) Name Description DDR2CI Controller Idle Status. 0 = Controller busy performing access or auto-refresh 1 = Controller idle DDR2SRA Self-Refresh Active. 0 = Not in self-refresh mode 1 = Active DDR2PUA Power-Up Sequence Active.
Page 865 Registers Reference Controller Status Register 1 (DDR2STAT1) This register reports the DDR2 bank active/idle status. This register is shown in Figure A-15 and described in Table A-19. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Field (23–16) Bit Field (31–24) External Bank 2...
Page 866 ADSP-2146x External Port Registers Table A-19. DDR2STAT1 Register Bit Descriptions (RO) (Cont’d) Bit Field Field Name Description 23–16 External Bank 2 External Bank 0 Active/Precharge State. Status xxxxxxx1 = Internal bank 0 in open state xxxxxxx0 = Internal bank 0 in precharge state xxxxxx1x = Internal bank 1 in open state xxxxxx0x = Internal bank 1 in precharge state …...
Page 867 Registers Reference Table A-20. DLL0CTL1 Register Bit Descriptions (RW) Name Description 8–0 Reserved RESETDLL Reset DLL Control Logic. Active high, when active, it resets the DLL control logic only, including the 90 degree DQS shifters. 0 = No effect 1 = Reset DLL0 control logic RESETDAT Reset Data Capture Logic.
Page 868 ADSP-2146x External Port Registers Table A-21. DLL1CTL1 Register Bit Descriptions (RW) Name Description 8–0 Reserved RESETDLL Reset DLL Control Logic. Active high, when active, it resets the DLL control logic only, including the 90 degree DQS shifters. 0 = No effect 1 = Reset DLL1 control logic RESETDAT Reset Data Capture Logic.
Page 869 Registers Reference DDR2 Pad Control Register 0 (DDR2PADCTL0) register shown in Figure A-18 and described in DDR2PADCTL0 Table A-23 includes the programmable parameters associated with the DDR2 pads. DATA DDR2CLK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DQS_PWD DDR2CLK_PWD...
Page 870 ADSP-2146x External Port Registers DDR2 Pad Control Register 1 (DDR2PADCTL1) register shown in Figure A-19 and described in DDR2PADCTL1 Table A-24 includes the programmable parameters associated with the DDR2 Command ( ) and Address pad control. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CMD_PWD...
Page 871 Registers Reference ADSP-2147x, ADSP-2148x External Port Registers The registers in the following sections are specific to the ADSP-2147x and the ADSP-2148x external port and include the external port, the SDRAM controller, and AMI registers. External Port Control Register (EPCTL) The external port control register can be programmed to arbitrate the accesses between the processor core and DMA, and between different DMA channels.
Page 872 ADSP-2147x, ADSP-2148x External Port Registers Table A-25. EPCTL Register Bit Descriptions (RW) Name Description B0SD Select Bank 0 SDRAM. 0 = Bank 0 non-SDRAM 1 = Bank 0 SDRAM B1SD Select Bank 1 SDRAM. 0 = Bank 1 Non-SDRAM 1 = Bank 1 SDRAM B2SD Select Bank 2 SDRAM.
Page 873 Registers Reference Table A-25. EPCTL Register Bit Descriptions (RW) (Cont’d) Name Description 14–12 FRZCR Arbitration Freezing Length for CORE Accesses. 000 = No Freezing 001 = 4 Accesses 010 = 8 Accesses 011 = 16 Accesses 100 = 32 Accesses 101 = Page size (SDRAM only 110, 111 = Reserved 18–15...
Page 874 ADSP-2147x, ADSP-2148x External Port Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PREDIS Disable Predictive Reads Bus Idle Cycle RHC (20–18) AMIFLSH Read Hold Cycle AMI Buffer Flush 11 10 IC (16–14) AMIEN HC (13–11 AMI Enable...
Page 875 Registers Reference Table A-26. AMICTLx Register Bit Descriptions (RW) (Cont’d) Name Description PKDIS Disable Packing/Unpacking. 0 = 8/16-bit data received packed to 32-bit data. Similarly, 32-bit data to be transmitted is unpacked to four 8-bit data. 1 = 8/16-bit data received zero-filled, for transmitted data only 8-bit LSB part of the 32-bit data is written to external memory.
Page 876 ADSP-2147x, ADSP-2148x External Port Registers Table A-26. AMICTLx Register Bit Descriptions (RW) (Cont’d) Name Description 16–14 Bus Idle Cycle. Default Idle cycles are inserted whenever read to write in a bank or read to read between two external banks or a read to the SDC happened.
Page 877 Registers Reference AMI Status Register (AMISTAT) This 32-bit register provides status information for the AMI interface and can be read at any time. This register is shown in Figure A-22 described in Table A-27. 11 10 AMIMS AMIS External Bus Master External Interface Status Figure A-22.
Page 878 ADSP-2147x, ADSP-2148x External Port Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SDADDRMODE X16DE SDRAM External Data Path Width Address Map Mode SDTWR (18–17) PGSZ 128 SDRAM tWR Specification Page size is 128 bits SDORF SDRAW (29–27) Optional Refresh...
Page 879 Registers Reference Table A-28. SDCTL Register Bit Descriptions (RW) Name Description 1–0 SDCL SDRAM CAS Latency. 2–3 SDCLK cycles. The delay in clock cycles between when the SDRAM detects the read command and when it provides the data at its output pins. 00, 01 = Reserved 10 = 2 cycles 11 = 3 cycles...
Page 880 ADSP-2147x, ADSP-2148x External Port Registers Table A-28. SDCTL Register Bit Descriptions (RW) (Cont’d) Name Description 13–12 SDCAW SDRAM Bank Column Address Width. SDRAM Page Size. 00 = 8 bits 01 = 9 bits 10 = 10 bits 11 = 11 bits SDPSS SDRAM Power-Up Sequence Start.
Page 881 Registers Reference Table A-28. SDCTL Register Bit Descriptions (RW) (Cont’d) Name Description Force Load Mode Register Command. This command performs a (WO) load mode register command immediately. 0 = No effect 1 = Force MR SDBUF Pipeline Option with External Register Buffer. 0 = No buffer option 1 = External SDRAM CTL/ADDR control buffer enable 26–24...
Page 882 ADSP-2147x, ADSP-2148x External Port Registers 11 10 SDPEND SDCI SDRAM Pipeline Status SDRAM Controller Idle SDSRA SDRS SDRAM Self-Refresh Active SDRAM In Reset State SDPUA SDRAM Power-Up Active Figure A-24. SDSTAT0 Register Table A-29. SDSTAT0 Register Bit Descriptions (RO) Name Description SDCI SDC Idle.
Page 883 Registers Reference Controller Status Register 1 (SDSTAT1) This register reports the SDRAM bank active/idle status. This register is shown in Figure A-25 and described in Table A-30. 11 10 Bit Field (15–12) Bit Field (3–0) External Bank 1 External Bank 0 Status Bit Field (11–8) Status...
Page 884 ADSP-2147x, ADSP-2148x External Port Registers Table A-30. SDSTAT1 Register Bit Descriptions (RO) (Cont’d) Bit Field Field Name Description 23–16 External Bank 2 External Bank 0 Active/Precharge State. Status xxx1 = Internal bank 0 in open state xxx0 = Internal bank 0 in precharge state xx1x = Internal bank 1 in open state xx0x = Internal bank 1 in precharge state …...
Page 885 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SDROPT SDMODIFY(20–17) SDRAM Optimization Used for Predictive Addressing 11 10 RDIV (11–0) Refresh Divider Count Figure A-26. SDRRC Register Table A-31. SDRRC Register Bit Descriptions (RW) Name Description 11–0...
Page 886 External Port DMA Control Registers (DMACx) External Port DMA Control Registers (DMACx) registers control the DMA function of their respective DMA DMAC0–1 channels. These registers apply to all processors described in this manual and are shown in Figure A-27 and described in Table A-32.
Page 887 Registers Reference Table A-32. External Port DMA Register Bit Descriptions (RW) Name Description DMA Enable. 0 = External port channel x DMA is disabled 1 = Enable External port DMA for channel x TRAN DMA Direction. Determines the DMA data direction. For internal to internal transfers, TRAN must be set.
Page 888 External Port DMA Control Registers (DMACx) Table A-32. External Port DMA Register Bit Descriptions (RW) (Cont’d) Name Description TLEN Scatter/Gather (Tap List) DMA Enable. 0 = Disables the tap list based scatter/gather DMA 1 = Enables the tap list based scatter/gather DMA 11–10 Reserved INTIRT...
Page 889 Registers Reference Table A-32. External Port DMA Register Bit Descriptions (RW) (Cont’d) Name Description 25 (RO) DIRS DMA Transfer Direction Status. 0 = DMA direction is external reads 1 = DMA direction is external writes This is useful for delay line DMA where the transfer direction changes with the state of the DMA state machine.
Page 890 Peripheral Registers 11 10 EXTTXFR_DONE_MSK External Transfer Done Mask Link Buffer Enable LPIT_MSK LDEN Invalid Transmit Interrupt Mask Link Buffer DMA Enable DMACH_IRPT_MSK LCHEN Link Buffer DMA Chaining DMA Channel Interrupt Mask Enable LRRQ_MSK LTRAN Link Port Receive Request Mask Link Buffer Transfer LTRQ_MSK Direction...
Page 891 Registers Reference Table A-33. LCTLx Register Bit Descriptions (RW) (Cont’d) Name Description LRRQ_MSK Link Port Receive Request Mask. 0 = Mask 1 = Unmask DMACH_ DMA Channel Count Interrupt Mask. Must be set to generate inter- IRPT_MSK rupt if DMA count is zero and is compatible with traditional SHARC processors.
Page 892 Peripheral Registers Table A-34. LSTATx Register Bit Descriptions (RO) Name Description 0 (ROC) LTRQ Link Port Transmit Request Status. 1 (ROC) LRRQ Link Port Receive Request Status. 2 (ROC) DMACH_IRPT DMA Channel Count Interrupt. 3 (ROC) LPIT Link Port Invalid Transmit Interrupt. 4 (ROC) EXTTXFR_DONE External Transfer Done Interrupt.
Page 893 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MTMDMA1ACT MTMDMA0ACT (WO) Memory Read DMA Status Memory Write DMA Status 11 10 MTMDEN MTMFLUSH (WOC) MTM DMA Enable 1=Flush the FIFO and reset the 0=Disable read/write pointers 1=Enable...
Page 894 Peripheral Registers Writes to the enable and disable bit-pairs for a PWM group works as follows. = 0, = 0 – No action PWM_DISx PWM_ENx = 0, = 1 – Enable the PWM group PWM_DISx PWM_ENx = 1, = x – Disable the PWM group PWM_DISx PWM_ENx For reads, the interpretation is as follows.
Page 895 Registers Reference Table A-35. PWMGCTL Register Bit Descriptions (RW) (Cont’d) Name Function 8, 10, 12, 14 PWM_SYNCENx PWM Group x Enable 9, 11, 13, 15 PWM_SYNCDISx PWM Group xDisable Global Status Register (PWMGSTAT) This register provides the status of each PWM group (Table A-36).
Page 896 Peripheral Registers Table A-37. PWMCTLx Register Bit Descriptions (RW) Name Description PWM_ALIGN Align Mode. 0 = Edge-aligned. The PWM waveform is left-justified in the period window. 1 = Center-aligned. The PWM waveform is symmetrical. PWM_PAIR Pair Mode. 0 = Non-paired mode. The PWM generates independent signals (for example xH, xL) 1 = Paired mode.
Page 897 Registers Reference Status Registers (PWMSTATx) These 16-bit registers, described in Table A-38, report the status of the phase and mode for each PWM group. Table A-38. PWMSTATx Register Bit Descriptions (RO) Name Description PWM_PHASE PWM Phase Status. Set during center aligned mode in the sec- ond half of each PWM period.
Page 898 Peripheral Registers Table A-39. PWMSEGx Register Bit Descriptions (RW) (Cont’d) Name Description PWM_AH Channel A High Disable. Enables or disables the channel A output signal. 0 = Enable 1 = Disable PWM_AL Channel A Low Disable. Enables or disables the channel A output signal.
Page 899 Registers Reference Table A-40. PWMPOLx Register Bit Descriptions (RW) (Cont’d) Name Description PWM_POL1AH Channel AH Polarity 1. 0 = Channel AH polarity 0 1 = Channel AH polarity 1 (default) PWM_POL0AH Channel AH Polarity 0. 0 = Channel AHpolarity 0 1 = Channel AH polarity 1 (default) PWM_POL1BL Channel BL Polarity 1.
Page 900 Peripheral Registers Duty Cycle Low Side Registers (PWMALx, PWMBLx) The 16-bit duty-cycle control registers (RW) directly control the AL/BL duty cycles (two’s-complement) of the non-paired PWM signals. These can be different from the AH/BH cycles. Dead Time Registers (PWMDTx) These 16-bit RW registers set up a short time delay (10-bit, unsigned) between turning off one PWM signal and turning on its complementary signal.
Page 901 Registers Reference General Control Register (FFTCTL1) The global control register ( ) shown in Figure A-33 and described FFTCTL1 Table A-41 is used to enable, start, and reset the FFT module. It is also used to enable DMA and debug operation. 31 30 29 28 27 26 25 24 23 22...
Page 902 Peripheral Registers Table A-42. FFTCTL1 Register Bit Descriptions (RW) (Cont’d) Bits Name Description FFT_DBG Debug Mode Enable. 0 = Disable 1 = Enable 31–7 Reserved Control Register (FFTCTL2) The FFT control register, shown in Figure A-34 and described in Table A-43, is used to set up individual FFT parameters (such as length) and how the module process the FFT, such as data packing.
Page 903 Registers Reference Table A-43. FFTCTL2 Register Bit Descriptions (RW) Bits Name Description FFT_RPT Accelerator Repeat. If this bit is set and the program needs to change the parameters of the FFT (such as length), first clear the FFT_EN and FFT_START bits in the FFTCTL1. Next change the FFT parameters as needed.
Page 904 Peripheral Registers Multiplier Status Register (FFTMACSTAT) register, described in Table A-44, can be written only in FFT_MACSTAT debug mode. The status bits are sticky and are cleared when read. Table A-44. FFT_MACSTAT Register Bit Descriptions (ROC) Bits Name Description FFT_NAN FFT_DENORM Bits 3–0 follow the IEEE STD for floating point num- bers.
Page 905 Registers Reference Debug Registers (FFTDADDR, FFTDDATA) Bits 31–0 is the register correspond to the data to be read or FFT_DDATA written. When a data write is performed first this register is loaded with data which needs to be written, then the register is loaded FFT_DADDRESS with the write address of the location.
Page 906 Peripheral Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIR_RND (16–14) Rounding Mode Select For Floating-point Mode 11 10 FIR_EN FIR_RND (16–14) Accelerator Enable Rounding Mode FIR_CH (5–1) FIR_TC Number of Channels Two’s-Complement Format FIR_DMAEN FIR_FXD...
Page 907 Registers Reference Table A-47. FIRCTL1 Register Bit Descriptions (RW) (Cont’d) Bits Name Description FIR_CCINTR Channel Complete Interrupt. 0 = Interrupt is generated only when all channels are done (default) 1= Interrupt is generated after each channel is done FIR_FXD Fixed-Point Accelerator Select. 0 = 32-bit IEEE floating-point 1 = 32-bit fixed point FIR_TC...
Page 908 Peripheral Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIR_UPSAMP WINDOW (23–14) Up Sampling Enable Window Size FIR_SRCEN FIR_RATIO Sample Rate Conversion Up/Down Sampling Ratio Enable 11 10 WINDOW (23–14) TAPLEN (11–0) Window Size Tap Length Figure A-36.
Page 909 Registers Reference FIR MAC Status Register (FIRMACSTAT) This register, shown in Figure A-37 and described in Table A-49, provides the status of MAC operations. The status of all four multipliers/adders are available separately for programs to poll. In fixed-point mode only the bits are used (all other bits are reserved).
Page 910 Peripheral Registers Table A-49. FIRMACSTAT Register Bit Descriptions (RO) (Cont’d) Bits Name Description FIR_MACMRZ1 Multiplier Result Zero. Set if multiplier 1 results is zero. FIR_MACMRI1 Multiplier Result Infinity. Set if multiplier 1 results is infinity. FIR_MACMINV1 Multiply Invalid. Set if multiplier 1 multiply operation is invalid.
Page 911 Registers Reference FIR DMA Status Register (FIRDMASTAT) The information provided by this register, shown in Figure A-38 described in Table A-50, are, chain pointer loading, coefficient DMA, data preload DMA, processing in progress, window complete, all channels complete. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...
Page 912 Peripheral Registers Table A-50. FIRDMASTAT Register Bit Descriptions (RO) Bits Name Description 11–7 CURCHNL Current Channel. Channel that is being processed in the TDM slot. Zero indicates the last slot. 13–12 CURITER Current MAC Iteration. Current MAC iteration in multi iteration mode.
Page 913 Registers Reference Table A-51. FIRDEBUGCTL Register Bit Descriptions (RW) Bits Name FIR_DBGMODE Debug Mode Enable. 0 = Disable 1 = Enable For local memory access, the FIRCTL1 register can be cleared. FIR_HLD Hold Or Single Step. The function of this bit is based on the FIR_DBGMEM bit setting.
Page 914 Peripheral Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IIR_RND (16–14) Rounding Mode Select For Floating-point Mode 11 10 IIR_EN IIR_RND (16–14) Accelerator Enable Rounding Mode NCH (5–1) IIR_FORTYBIT Number of Channels 40-Bit Floating-Point Select IIR_DMAEN IIR_CCINTR...
Page 915 Registers Reference Table A-52. IIRCTL1 Register Bit Descriptions (RW) (Cont’d) Bits Name Description IIR_CCINTR Channel Complete Interrupt. 0 = Interrupt is generated only when all channels are done (default) 1 = Interrupt is generated after each channels is done (default) IIR_FORTYBIT 40-Bit Floating-Point Format Select.
Page 916 Peripheral Registers IIR Channel Control Register (IIRCTL2) register, shown in Figure A-41 and described in Table A-53, IIRCTL2 is used to configure the channel specific parameters. These include num- ber of biquads and window size. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IIR_WINDOW (23–14)
Page 917 Registers Reference IIR MAC Status Register (IIRMACSTAT) register, shown in Figure A-42 and described in IIRMACSTAT Table A-54, provides the status of MAC operations. 11 10 IIR_MRZ IIR_MRI IIR_AINV IIR_MINV IIR_ARI IIR_ARZ Figure A-42. IIRMACSTAT Register Table A-54. IIRMACSTAT Register Bit Descriptions (RO) Bits Name Description...
Page 918 Peripheral Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 11 10 IIR_DMACPL IIR_DMAURCHNL (11–7) Chain Pointer Load Status Current Channel IIR_DMACNDKLD IIR_DMAACDONE Coefficient Loading All Channels Done IIR_DMAPPGS IIR_DMAWDONE MAC Processing in Processing of Current Channel Done Process IIR_DMASVDK...
Page 919 Registers Reference IIR Debug Registers (IIRDEBUGCTL, IIRDEBUGADDR) register, shown in Figure A-44 and described in IIRDEBUGCTL Table A-56, controls the debug mode operation of the IIR accelerator. Note that these registers should only be used in debug mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...
Page 920 Peripheral Registers Table A-56. IIRDEBUGCTL Register Bit Descriptions (RW) (Cont’d) Bits Name Description IIR_ADRINC Address Auto Increment. If this bit is set, the address register auto increments on IIRDBGWRDATA_H/ IIRDBGWRDATA_L writes and IIRDBGRDDATA_H/ IIRDBGRDDATA_L reads. 31–6 Reserved Media Local Bus Registers The registers in this section are used to program and get status informa- tion for the MLB interface and the specific channels used.
Page 921 Registers Reference Table A-57. MLB_DCCR Register Bit Descriptions (RW) Name Description 7–0 MLB Device Address. Determines the unique device address (DA) for ADSP-214xx MediaLB device. MLB device address is 16 bits. Bits 15– 9 and LSB are always zero. Only bits 8–1 vary and they are defined by MLB_DCCR bits 7–0.
Page 922 Peripheral Registers Table A-57. MLB_DCCR Register Bit Descriptions (RW) (Cont’d) Name Description 29–28 MLB Clock Select. 00 = 256Fs – supports 8 quadlets per frame 01 = 512Fs – supports 16 quadlets per frame 10 = 1024Fs – supports 32 quadlets per frame 11 = reserved Loopback Mode Enable.
Page 923 Registers Reference Table A-58. MLB_SSCR Register Bit Descriptions (RW1C) Name Description System Detects Reset Command. When set, indicates MLB device has received MLBReset system command. SDNL System Detects Network Lock. When set, indicates the MLB device has received Most lock system command. SDNU System Detects Network Unlock.
Page 924 Peripheral Registers Table A-59. MLB_SDCR Register Description (RO) Name Description 31–0 SDATA System Channel Data. System Mask Configuration Register (MLB_SMCR) This register, described in Table A-60, allows system software to mask sys- tem status interrupts. When a mask bit is set, the corresponding system channel interrupt is masked.
Page 925 Registers Reference Table A-60. MLB_SMCR Register Bit Descriptions (RW) (Cont’d) Name Description SMSC System Masks Subcommand. When set, this bit masks system interrupts for MlbSubCmd (0xE6) system command. SMML System Masks MLB Lock. When set, this bit masks system interrupts generated when MLB lock is detected.
Page 926 Peripheral Registers Synchronous Base Address Register (MLB_SBCR) , described in Table A-62, holds the base address of the sys- MLB_SBCR tem memory buffers of all synchronous channels in the device. Table A-62. MLB_SBCR Register Bit Descriptions (RW) Name Description 4–0 STBA Synchronous transmit base address for DMA mode 15–5...
Page 927 Registers Reference Control Base Address Register (MLB_CBCR) register, described in Table A-64, hold the base address of MLB_CBCR the system memory buffers of all control channels in the device. Table A-64. MLB_CBCR Register Bit Descriptions (RW) Name Description 4–0 CTBA Control transmit base address for DMA mode 15–5 Reserved...
Page 928 Peripheral Registers Channel Control Registers (MLB_CECRx) These registers define the basic attributes of a given logical channel, such as the channel enable, channel direction, and channel address. The defini- tion of the bit fields in these registers vary by the selected channel type. Figure A-48 Table A-66 provide information for for asynchronous...
Page 929 Registers Reference Table A-66. MLB_CECRx Register Bit Descriptions for Asynchronous and Control Channels (RW) Name Description 7–0 Channel Address. These bits determine the channel address associated with this logical channel. MLB channel address is 16 bits; bits 15–9 and LSB are always zero. Only bits 8–1 vary and they are defined by MLB_CECRx bits 7–0.
Page 930 Peripheral Registers Table A-66. MLB_CECRx Register Bit Descriptions for Asynchronous and Control Channels (RW) (Cont’d) Name Description MASK4 Mask Buffer Error. When set, masks buffer error channel interrupts for this logical channel. Reserved MASK6 Mask Lost Frame Synchronization. When set, masks lost frame syn- chronization channel interrupts for this logical channel.
Page 931 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Channel x Enable MASK (23–16) Channel x Interrupt Mask CTRAN Channel x Transmit Select Channel x Mode Select CTYPE (29–28) Channel x Type Select Frame Synchronization Enable 11 10...
Page 932 Peripheral Registers Table A-67. MLB_CECRx Register Bit Descriptions for Synchronous Channels (RW) Name Description MASK0 Mask Protocol Error. When set, masks protocol error channel inter- rupts for this logical channel. This bit valid for all Rx channel types. This is valid for asynchronous and control Tx channels only. MASK1 Mask Detect Break.
Page 933 Registers Reference Table A-67. MLB_CECRx Register Bit Descriptions for Synchronous Channels (RW) Name Description 29–28 CTYPE Channel x Type Select. 00 = Synchronous (default) 01 = Reserved 10 = Asynchronous 11 = Control CTRAN Channel x Transmit Select. 0 = Receive (default) 1 = Transmit Channel x Enable.
Page 934 Peripheral Registers Channel Status Configuration Registers (MLB_CSCRx) This register, shown in Figure A-50 and described in Table A-68, shows the status of the current and previous buffer for the given logical channel. For all bits a 1 means the condition exists. 31 30 29 28 27 26 25 24 23 22...
Page 935 Registers Reference Table A-68. MLB_CSCRx Register Description (RO) Name Description STS0 Current Buffer Protocol Error. Indicates that either a TX channel has detected an RxStatus of ReceiverProtocolError (72h), an RX channel has detected an invalid command for a given channel type, or an additional ControlStart (30h) or Async- Start (20h) command has been received while in the middle of a packet.
Page 936 Peripheral Registers Table A-68. MLB_CSCRx Register Description (RO) (Cont’d) Name Description STS4 Buffer Error. Indicates that either a TX channel has detected a buffer underflow (attempt to pop data from an empty buffer), or an RX channel has detected a buf- fer overflow (attempt to push data onto a full buffer).
Page 937 Registers Reference Table A-68. MLB_CSCRx Register Description (RO) (Cont’d) Name Description STS10 Previous Buffer Done. Indicates that the last quadlet of the Previous Buffer has (DMA) been successfully transmitted or received. The setting of this bit generates a mask- able channel interrupt to system software. This bit is valid for all channel types. Reserved in I/O mode.
Page 938 Peripheral Registers The 5-bit offset of the DMA address comes from the base address registers. Table A-69. MLB_CCBCRx Register Bit Descriptions (RO) Name Description 1–0 Reserved for other channel types 15–2 Buffer Final Address. 17–16 Reserved for other channel types 31–18 Buffer Current Address.
Page 939 Registers Reference equally by all 31 channels with four words for each channel. The buffer depth can be up to 124 words (quadlets), when only one channel is used. Table A-71. MLB_LCBCRx Register Description (RW) Name Description 12–0 Buffer Start Address. Determines the starting address (in quadlets/4) of the channel buffer for the logical channel x.
Page 940 Peripheral Registers Watchdog Timer Registers The following sections provide bit descriptions for the registers associated with the watchdog timer. Control (WDTCTL) The watchdog control register ( ), is a 32-bit system mem- WDTCTL ory-mapped register used to configure the watchdog timer. WDTCTL protected against accidental writes from the processor core by the watch- dog unlock register (...
Page 941 Registers Reference Table A-72. WDTSTATUS Register Bit Descriptions (RO) Name Description 0 (W1C) WDRO Watchdog Expired. Indicates that DSP core attempted to write to WDT configuration space without an unlock “command”. Bit is set when the above exception occurs. Software can determine whether the watchdog has expired by interrogating this bit.
Page 942 Peripheral Registers updated when the WDT is disabled and WDT configuration space is unlocked by programming the command in the register. WDTUNLOCK Table A-73. WDTTRIP Register Bit Descriptions (RW) Name Description 3–0 TRIPVAL Current Value of Trip Counter. This is the trip counter value, programmable from 0 to 15.
Page 943 Registers Reference Table A-74. WDTCLKSEL Register Bit Descriptions (RW) (Cont’d) Name Description OSCPWRDWN Internal RC Oscillator Power Down. 0 = Oscillator is powered up 1 = Oscillator is powered down OSCRST Internal RC Oscillator Reset. 0 = Oscillator is reset 1 = Oscillator out of reset Period (WDTCNT) register, shown in Table 3, holds the 32-bit unsigned count...
Page 944 DAI Signal Routing Unit Registers DAI Signal Routing Unit Registers The digital applications interface is comprised of a group of peripherals and the signal routing unit (SRU). These register groups are described in the sections that follow. Clock Routing Control Registers (SRU_CLKx, Group A) These registers (see Figure A-52...
Page 945 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRC2_CLK_OP_I (29–25) SRC1_CLK_OP_I (19–15) Sample Rate Converter 2 Sample Rate Converter 1 Clock Output Input Clock Output Input SRC2_CLK_IP_I (24–20) Sample Rate Converter 2 Clock Input Input 11 10 SRC1_CLK_OP_I (19–15)
Page 946 DAI Signal Routing Unit Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDP6_CLK_I (con’t) (19–15) Input Data Port Channel DIT_HFCLK_I (29–25) 6 Clock Input SPDIF Oversampling Clock Input IDP7_CLK_I (24–20) Input Data Port Channel 7 Clock Input 11 10 IDP6_CLK_I (19–15)
Page 947 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCG_EXTD_I PCG_SYNC_CLKD_I Precision Clock Generator Precision Clock Generator External Clock D Input Clock D Sync Input PCG_EXTC_I Precision Clock Generator External Clock C Input 11 10 PCG_SYNC_CLKD_I SPORT6_CLK_I...
Page 948 DAI Signal Routing Unit Registers Table A-75. Group A Sources – Serial Clock (Cont’d) Selection Code Source Signal Description (Source Selection) 01101 (0xD) DAI_PB14_O Pin Buffer 14 01110 (0xE) DAI_PB15_O Pin Buffer 15 01111 (0xF) DAI_PB16_O Pin Buffer 16 10000 (0x10) DAI_PB17_O Pin Buffer 17 10001 (0x11)
Page 949 Registers Reference Serial Data Routing Registers (SRU_DATx, Group B) The serial data routing control registers (see Figure A-58 through Figure A-64) route serial data to the serial ports (A and B data channels) and the input data port. Each of the data inputs specified are connected to a data source based on the 6-bit values shown in Table A-76.
Page 950 DAI Signal Routing Unit Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRC2_DAT_IP_I (29–24) SRC0_DAT_IP_I (17–12) (con’t) Sample Rate Converter 2 Sample Rate Converter 0 Data Input Input Data Input Input SRC1_DAT_IP_I (23–18) Sample Rate Converter 1 Data Input Input...
Page 951 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDP1_DAT_I (17–12) (con’t) IDP3_DAT_I (29–24) Input Data Port 1 Data Input Input Data Port 3 Data Input IDP2_DAT_I (23–18) Input Data Port 2 Data Input 11 10 IDP1_DAT_I (17–12)
Page 952 DAI Signal Routing Unit Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPORT7_DA_I SPORT7_DB_I Serial Port 7 Data Channel A Input Serial Port 7 Data Channel BA Input 11 10 SPORT7_DA_I Serial Port 7 Data Channel A Input SPORT6_DA_I Serial Port 6 Data...
Page 953 Registers Reference Table A-76. Group B Sources – Serial Data (Cont’d) Selection Code Source Signal Description (Source Selection) 001111 (0xF) DAI_PB16_O Pin Buffer 16 010000 (0x10) DAI_PB17_O Pin Buffer 17 010001 (0x11) DAI_PB18_O Pin Buffer 18 010010 (0x12) DAI_PB19_O Pin Buffer 19 010011 (0x13) DAI_PB20_O Pin Buffer 20...
Page 954 DAI Signal Routing Unit Registers Table A-76. Group B Sources – Serial Data (Cont’d) Selection Code Source Signal Description (Source Selection) 101100(0x2C) SPORT6_DA_O SPORT 6A Data 101101(0x2D) SPORT6_DB_O SPORT 6B Data 101110(0x2E) SPORT7_DA_O SPORT 7A Data 101111(0x2F) SPORT7_DB_O SPORT 7B Data 110000(0x30) DIT_O SPDIF TX BiphaseStream...
Page 955 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPORT5_FS_I (29–25) SPORT3_FS_I (19–15) (con’t) Serial Port 3 Frame Serial Port 5 Frame Sync Input Sync Input SPORT4_FS_I (24–20) Serial Port 4 Frame Sync Input 11 10 SPORT3_FS_I (19–15)
Page 956 DAI Signal Routing Unit Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDP0_FS_I or PDAP_HOLD_I (19–15) IDP2_FS_I (29–25) (con’t) Input Data Port Channel 2 Input Data Port Channel Frame Sync Input 0 Frame Sync Input IDP1_FS_I (24–20) Input Data Port Channel 1...
Page 957 Registers Reference Table A-77. Group C Sources – Frame Sync Selection Code Source Signal Description (Source Selection) 00000 (0x0) DAI_PB01_O Pin Buffer 1 00001 (0x1) DAI_PB02_O Pin Buffer 2 00010 (0x2) DAI_PB03_O Pin Buffer 3 00011 (0x3) DAI_PB04_O Pin Buffer 4 00100 (0x4) DAI_PB05_O Pin Buffer 5...
Page 958 DAI Signal Routing Unit Registers Table A-77. Group C Sources – Frame Sync (Cont’d) Selection Code Source Signal Description (Source Selection) 11010 (0x1A) DIR_FS_O SPDIF RX Frame Sync Output 11011 (0x1B) Reserved 11100 (0x1C) PCG_FSA_O Precision Frame Sync A Output 11101 (0x1D) PCG_FSB_O Precision Frame Sync B Output...
Page 959 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_PB07_I (20–14) (con’t) DAI_PB08_I (27–21) DAI Pin Buffer 7 Input DAI Pin Buffer 8 Input 11 10 DAI_PB07_I (20–14) DAI_PB05_I (6–0) DAI_PB06_I (13–7) DAI Pin Buffer 5 Input DAI Pin Buffer 6 Input Figure A-71.
Page 960 DAI Signal Routing Unit Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_PB20_I_INVERT DAI_PB19_I (20–14) (con’t) DAI_PB19_I_INVERT DAI Pin Buffer 19 Input DAI_PB20_I (27–21) DAI Pin Buffer 20 Input 11 10 DAI_PB19_I (20–14) DAI_PB17_I (6–0) DAI_PB18_I (13–7)
Page 961 Registers Reference Table A-78. Group D Sources – Pin Signal Assignments (Cont’d) Selection Code Source Signal Description (Source Selection) 0001101 (0xD) DAI_PB14_O Pin Buffer 14 0001110 (0xE) DAI_PB15_O Pin Buffer 15 0001111 (0xF) DAI_PB16_O Pin Buffer 16 0010000 (0x10) DAI_PB17_O Pin Buffer 17 0010001 (0x11) DAI_PB18_O...
Page 962 DAI Signal Routing Unit Registers Table A-78. Group D Sources – Pin Signal Assignments (Cont’d) Selection Code Source Signal Description (Source Selection) 0100111 (0x27) SPORT1_FS_O SPORT 1 Frame Sync 0101000 (0x28) SPORT2_FS_O SPORT 2 Frame Sync 0101001 (0x29) SPORT3_FS_O SPORT 3 Frame Sync 0101010 (0x2A) SPORT4_FS_O SPORT 4 Frame Sync...
Page 963 Registers Reference Table A-78. Group D Sources – Pin Signal Assignments (Cont’d) Selection Code Source Signal Description (Source Selection) 1000011 (0x43) DIR_CLK_O SPDIF_RX Clock Output 1000100 (0x44) DIR_TDMCLK_O SPDIF_RX TDM Clock Output 1000101 (0x45) DIT_O SPDIF TX Biphase Encoded Data Output 1000110 (0x46) SPORT0_TDV_O SPORT0 Transmit Data Valid Output...
Page 964 DAI Signal Routing Unit Registers Miscellaneous Signal Routing Registers (SRU_MISCx, Group E) Miscellaneous register A allows programs to route to the DAI interrupt latch, PBEN input routing, or input signal inversion. In contrast, miscel- laneous register B allows programs to only route to the DAI interrupt latch (see Figure A-75 Figure...
Page 965 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_INT_25_I DAI_INT_27_I DAI Interrupt 25 DAI Interrupt 27 DAI_INT_26_I DAI Interrupt 26 11 10 DAI_INT_25_I DAI_INT_22_I DAI Interrupt 25 DAI Interrupt 22 DAI_INT_24_I DAI_INT_23_I DAI Interrupt 24...
Page 966 DAI Signal Routing Unit Registers Table A-79. Group E Sources – Miscellaneous Signals (Cont’d) Selection Code Source Signal Description (Output Source Selection) 01111 (0xF) DAI_PB16_O Pin Buffer 16 Output 10000 (0x10) DAI_PB17_O Pin Buffer 17 Output 10001 (0x11) DAI_PB18_O Pin Buffer 18 Output 10010 (0x12) DAI_PB19_O Pin Buffer 19 Output...
Page 967 Registers Reference DAI Pin Buffer Enable Registers (SRU_PBENx, Group F) The pin enable control registers (see Figure A-77 through Figure A-80, Table A-80) activate the drive buffer for each of the 20 DAI pins. When the pins are not enabled (driven), they can be used as inputs. 31 30 29 28 27 26 25 24 23 22...
Page 968 DAI Signal Routing Unit Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PBEN13_I PBEN15_I PBEN14_I DAI Port 15 DAI Port 14 Pin Buffer Enable Input Pin Buffer Enable Input 11 10 PBEN11_I DAI Port 11 PBEN13_I...
Page 969 Registers Reference Table A-80. Group F Sources – Pin Output Enable Selection Code Source Signal Description (Output Source Selection) 000000 (0x0) Logic Level Low (0) 000001 (0x1) HIGH Logic Level High (1) 000010 (0x2) MISCA0_O Miscellaneous Control A0 Output 000011 (0x3) MISCA1_O Miscellaneous Control A1 Output 000100 (0x4)
Page 970 DAI Signal Routing Unit Registers Table A-80. Group F Sources – Pin Output Enable (Cont’d) Selection Code Source Signal Description (Output Source Selection) 011010 (0x1A) SPORT4_DA_PBEN_O SPORT 4 Data Channel A Output Enable 011011 (0x1B) SPORT4_DB_PBEN_O SPORT 4 Data Channel B Output Enable 011100 (0x1C) SPORT5_CLK_PBEN_O SPORT 5 Clock Output Enable...
Page 971 Registers Reference DAI Shift Register Routing Registers (Group G, ADSP-2147x) The pin enable control registers (see Figure A-81, Figure A-82, and Table A-81, Table A-82) activate the drive buffer for each of the 20 DAI pins. When the pins are not enabled (driven), they can be used as inputs. Clock Routing Register (SRU_CLK_SHREG) The shift register’s input signals can come from...
Page 972 DAI Signal Routing Unit Registers Table A-81. Group G Sources – Shift Register Clock Routing (Cont’d) Selection Code Source Signal Description (Output Source Selection) 01000 (0x8) SPORT6_CLK_O Sport 6 Clock Output 01001 (0x9) SPORT7_CLK_O Sport 7 Clock Output 01010 (0xA) SPORT0_FS_O Sport 0 Frame Sync Output 01011 (0xB)
Page 973 Registers Reference Data Routing Register (SRU_DAT_SHREG) The shift register’s input signal can come from either logic 0 , SR_SDI_I logic 1, SPORT0–7 data outputs, , or DAI pin buffers 1–8. SR_SDI Figure A-82 Table A-82 shows the list of sources and programmable options for the input signal.
Page 974 DAI Signal Routing Unit Registers Table A-82. Group G Sources – Shift Register Data Routing (Cont’d) Selection Code Source Signal Description (Output Source Selection) 01111 (0xF) SPORT6_DB_O Sport 6 Data Channel B 10000 (0x10) SPORT7_DA_O Sport 7 Data Channel A 10001 (0x11) SPORT7_DB_O Sport 7 Data Channel B...
Page 975 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_PB17 DAI_PB20 DAI_PB18 DAI_PB19 11 10 DAI_PB16 DAI_PB01 DAI_PB15 DAI_PB02 DAI_PB14 DAI_PB03 DAI_PB13 DAI_PB04 DAI_PB12 DAI_PB05 DAI_PB11 DAI_PB06 DAI_PB10 DAI_PB07 DAI_PB09 DAI_PB08 Figure A-83.
Page 976 Peripherals Routed Through the DAI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_31_INT IDP_DMA6_INT DAI_30_INT IDP_DMA7_INT DAI_29_INT SRC0_MUTE_INT SRC1_MUTE_INT DAI_28_INT SRC2_MUTE_INT DAI_27_INT SRC3_MUTE_INT DAI_26_INT DAI_22_INT DAI_25_INT DAI_23_INT DAI_24_INT 11 10 IDP_DMA5_INT DIR_VALID_INT IDP_DMA4_INT DIR_LOCK_INT...
Page 977 Registers Reference SPORT Divisor Registers (DIVx) These registers, shown in Figure A-85, allow programs to set the frame sync divisor and clock divisor. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FSDIV Frame Sync Divisor 11 10 CLKDIV...
Page 978 Peripherals Routed Through the DAI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DXS_A (31–30) Data Buffer Channel A Status Active Low Frame Sync DERR_A LAFS Channel A Error Status Late Frame Sync DXS_B (28–27) SDEN_A Data Buffer Channel B Status...
Page 979 Registers Reference Table A-84. SPCTLx Register Bit Descriptions (Standard Serial Mode) (RW) Name Description SPEN_A Enable Channel A Serial Port. 0 = Serial port A channel disabled 1 = Serial port A channel enabled 2–1 DTYPE Data Type Select. Selects the data type formatting for standard serial mode transmissions.
Page 980 Peripherals Routed Through the DAI Table A-84. SPCTLx Register Bit Descriptions (Standard Serial Mode) (RW) (Cont’d) Name Description PACK 16-Bit to 32-Bit Word Packing Enable. When PACK = 1, two succes- sive received words are packed into a single 32-bit word, and each 32-bit word is unpacked and transmitted as two 16-bit words.
Page 981 Registers Reference Table A-84. SPCTLx Register Bit Descriptions (Standard Serial Mode) (RW) (Cont’d) Name Description CKRE Clock Rising Edge Select. Determines clock signal to sample data and the frame sync selection. For sampling receive data and frame syncs, set- ting CKRE to 1 selects the rising edge of SPORTx_CLK. When CKRE is cleared (=0), the processor selects the falling edge of SPORTx_CLK for sampling receive data and frame syncs.
Page 982 Peripherals Routed Through the DAI Table A-84. SPCTLx Register Bit Descriptions (Standard Serial Mode) (RW) (Cont’d) Name Description SDEN_A Enable Channel A Serial Port DMA. 0 = Disable serial port channel A DMA 1 = Enable serial port channel A DMA SCHEN_A Enable Channel A Serial Port DMA Chaining.
Page 983 Registers Reference Table A-84. SPCTLx Register Bit Descriptions (Standard Serial Mode) (RW) (Cont’d) Name Description SPTRAN Data Direction Control. This bit controls the data direction of the serial port channel A and B signals. When cleared (= 0) the SPORT is configured to receive on both chan- nels A and B.
Page 984 Peripherals Routed Through the DAI Table A-84. SPCTLx Register Bit Descriptions (Standard Serial Mode) (RW) (Cont’d) Name Description DERR_A Channel A Error Status (sticky). Refer to DERR_B (RO) 31–30 DXS_A Channel A Data Buffer Status. Refer to DXS_B (RO) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...
Page 985 Registers Reference Table A-85. SPCTLx Register Bit Descriptions (I Left-Justified) (RW) Name Description SPEN_A Enable Channel A Serial Port. 0 = Serial port A channel disabled 1 = Serial port A channel enabled 3–1 Reserved 8–4 SLEN Serial Word Length Select. Selects the word length in bits. Word sizes can be from 8 bits to 32 bits.
Page 986 Peripherals Routed Through the DAI Table A-85. SPCTLx Register Bit Descriptions (I Left-Justified) (RW) (Cont’d) Name Description SDEN_A Enable Channel A Serial Port DMA. 0 = Disable serial port channel A DMA 1 = Enable serial port channel A DMA SCHEN_A Enable Channel A Serial Port DMA Chaining.
Page 987 Registers Reference Table A-85. SPCTLx Register Bit Descriptions (I Left-Justified) (RW) (Cont’d) Name Description DERR_B Channel B Error Status. SPORT configured as a transmitter, this bit (RO) provides transmit underflow status. As a transmitter, DERR_x bit indi- cates whether the SPORTx_FS signal (from an internal or external source) occurred while the DXS_x buffer was empty.
Page 988 Peripherals Routed Through the DAI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DXS_A (31–30) LMFS/L_FIRST Data Buffer Channel A Status Active Low Multichannel DERR_A Frame Sync Select/Channel Channel A Error status Order First SDEN_A DXS_B (28–27)
Page 989 Registers Reference Table A-86. SPCTLx Register Bit Descriptions (Packed and Multichannel) (RW) Name Description Reserved 2–1 DTYPE Data Type Select. Selects the data type formatting for multichan- nel/packed mode transmissions. For multichannel/packed mode A channels, selection of companding mode and MSB format are inclu- sive: Serial Data Channel A Type Formatting x0 = Right-justify, zero-fill unused MSBs...
Page 990 Peripherals Routed Through the DAI Table A-86. SPCTLx Register Bit Descriptions (Packed and Multichannel) (RW) (Cont’d) Name Description CKRE Clock Rising Edge Select. Determines clock signal to sample data and the frame sync selection. 0 = Falling edge 1 = Rising edge Reserved IMFS Internal Multichannel Frame Sync Select.
Page 991 Registers Reference Table A-86. SPCTLx Register Bit Descriptions (Packed and Multichannel) (RW) (Cont’d) Name Description SDEN_B Enable Channel B Serial Port DMA. 0 = Disable serial port channel B DMA 1 = Enable serial port channel B DMA SCHEN_B Enable Channel B Serial Port DMA Chaining. 0 = Disable serial port channel B DMA chaining 1 = Enable serial port channel B DMA chaining Reserved...
Page 992 Peripherals Routed Through the DAI Table A-86. SPCTLx Register Bit Descriptions (Packed and Multichannel) (RW) (Cont’d) Name Description DERR_B Channel B Error Status. When the SPORT is configured as a trans- (RO, mitter, this bit provides transmit underflow status. As a transmitter sticky) DERR_x bit indicates whether the SPORTx_FS signal (from an internal or external source) occurred while the DXS_x buffer was...
Page 993 Registers Reference SPORT Control 2 Registers (SPCTLNx) These registers (where x signifies SPORT 0 through 7) allow programs to set frame sync edge detection for I S compatibility. These registers also allow interrupts to be generated when transmit DMA count is expired or when the last bit of last word is shifted out.
Page 994 Peripherals Routed Through the DAI Table A-87. SPCTLNx Register Bit Descriptions (RW) (Cont’d) Name Description FSED Frame Sync Edge Detection. If set in multichannel mode, the SPORTs detect an active edge of an external frame sync and start transmitting/receiving only after that (even ifthe SPORTs are enabled at any instant of active frame sync).
Page 995 Registers Reference SPORT Multichannel Control Registers (SPMCTLx) The serial ports in the ADSP-214xx processors work individually, not in pairs. Therefore, each SPORT has its own multichannel control register. These registers are shown in Figure A-90 and described in Table A-88. Note that in ADSP-2136x SHARC processors there is one regis- SPMCTLxy...
Page 996 Peripherals Routed Through the DAI Table A-88. SPMCTLx Register Bit Descriptions (RW) Name Description MCEA Multichannel Mode Enable, A Channels. Packed and multichannel A modes only. One of two configuration bits that enable and disable multichannel mode on serial port channels. See OPMODE bit (17). 0 = Disable multichannel A operation 1 = Enable multichannel A operation/packed mode Note if MCEA bit is set, the corresponding SPEN_A bit in the SPCTL...
Page 997 Registers Reference Table A-88. SPMCTLx Register Bit Descriptions (RW) (Cont’d) Name Description 15–13 Reserved 22–16 (RO) CHNL Current Channel Selected. Identify the currently selected transmit channel slot (0 to 127). MCEB Multichannel B Mode Enable. Packed and multichannel B modes only.
Page 998 Peripherals Routed Through the DAI port is configured as transmitter. If the serial port is configured as the receiver it ignores the incoming data. SPORT Compand Registers (MTxCCSy or MRxCCSy) Each bit, 31–0, set (=1) in one of the four MTxCCS0 MTxCCS1 MTxCCS2...
Page 999 Registers Reference Table A-89. SPERRCTLx Register Bit Descriptions (RW) Name Description DERRA_EN Enable Channel A Error Detection. 0 = Disable 1 = Enable DERRB_EN Enable Channel B Error Detection. 0 = Disable 1 = Enable FSERR_EN Enable Frame Sync Error Detection. 0 = Disable 1 = Enable Reserved...
Page 1000 Peripherals Routed Through the DAI SPORT Error Status Register (SPERRSTAT) register checks the status of SPORT interrupts (see SPERRSTAT Figure A-92). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SP0 FSERR SP7 FSERR SP1 FSERR SP6 FSERR SP2 FSERR...

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Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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