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ADSP-SC58x DMC Register Descriptions
Priority ID Register 2
The
register is another register which allows transactions from selected masters that generate specific
DMC_PRIO2
SCB IDs to obtain higher priority than the transactions proceeding in the usual fashion. The contents of the register
are masked with the contents of the
elevated priority.
Figure 10-17: DMC_PRIO2 Register Diagram
Table 10-26: DMC_PRIO2 Register Fields
Bit No.
(Access)
31:0
ID2
(R/W)
10–54
DMC_PRIOMSK2
15
14
0
0
ID2[15:0] (R/W)
SCB ID2 that Requires Elevated Priority
31
30
0
0
ID2[31:16] (R/W)
SCB ID2 that Requires Elevated Priority
Bit Name
SCB ID2 that Requires Elevated Priority.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register to obtain a single SCB ID or a range of IDs that get
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
Description/Enumeration
5
4
3
2
1
0
0
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
0
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