Analog Devices ADSP-SC58 Series Hardware Reference Manual page 716

SPI Functional Description
pin is deasserted. The SPI uses the SPI_CTL.FCWM bits to control the FIFO status at which SPI_RDY deasser-
tion takes place. Flow control in slave mode is purely based on the FIFO status and does not depend on the word
counters.
The SPI Flow Control Timing in Master Mode figure illustrates this timing.
Figure 16-6: SPI Flow Control Timing in Master Mode.
Slave Select Operation
If the SPI is in slave mode, SPI_SS acts as the slave select input. When SPI is enabled as a master, SPI_SS can
serve as an error detection input for the SPI in a multi-master environment. The SPI_CTL.PSSE bit enables this
feature. When SPI_CTL.PSSE=1, the SPI_SS input is the master mode error input. Otherwise, SPI_SS is
ignored.
The SPI_SS signal is an active-low signal. The master asserts the signal during the transfer. The signal can be deas-
serted or remain asserted between transfers. When SPI_SS is deasserted, SPI_CLK and inputs are ignored, and
outputs are three-stated.
The slave select bits (SPI_SLVSEL.SSEL1 – SPI_SLVSEL.SSEL7) are used in a multiple-slave SPI environ-
ment. For example, if there are eight SPI devices in the system including a processor master, the master processor
can support the SPI mode transactions across the other seven devices. This configuration requires only one master
processor in this multi-slave environment.
16–10
SPI timing with flow-control stall, CPHA = 0
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
SPI_MOSI . . .
MSB
. . .
SPI_MISO
MSB
SPI_SS
SPI_RDY
SPI timing with flow-control stall, CPHA = 1
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
. . .
SPI_MOSI MSB
SPI_MISO
. . .
MSB
SPI_SS
SPI_RDY
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
LSB
LSB
LSB
LSB
MSB
MSB
MSB
MSB