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Shadow MR2 Register (DDR3)
The
register mirrors DDR3 SDRAM device Mode register 2 when the controller is operating in DDR3
DMC_MR2
mode. A write to this register triggers an extended "mode register set" command on the memory interface provided
the corresponding mask bit is set in the mask register. Else, only the mirror register is updated.
SRT (R/W)
Self Refresh Temperature Range
ASR (R/W)
Auto Self Refresh
Figure 10-14: DMC_MR2 Register Diagram
Table 10-23: DMC_MR2 Register Fields
Bit No.
(Access)
7
SRT
(R/W)
6
ASR
(R/W)
5:3
CWL
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
0
0
0
0
0
0
0
31
30
29
28
27
26
25
0
0
0
0
0
0
0
Bit Name
Self Refresh Temperature Range.
The DMC_MR2.SRT bit enables high temperature self-refresh rate.
Auto Self Refresh.
CAS Write Latency.
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
Description/Enumeration
0 Disable
1 Enable
0 Manual SR Reference (SRT)
1 ASR enable (Optional)
0 5 clock cycles
1 6 clock cycles
2 7 clock cycles
3 8 clock cycles
4 9 clock cycles
5 10 clock cycles
6 11 clock cycles
7 12 clock cycles
ADSP-SC58x DMC Register Descriptions
0
0
PASR (R/W)
Partial Array Self refresh
CWL (R/W)
CAS Write Latency
16
0
10–49
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