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The clock polarity and the clock phase could be identical for the master device and the slave device involved in the
communication link. The transfer format from the master can be changed between transfers to adjust for various
requirements of a slave device.
The SPI module uses the SPI_CTL.ASSEL bit to determine when the SPI hardware or software control the
SPI_SEL[n] line. When SPI_CTL.ASSEL=1, the slave select line must be set to the polarity set in the
SPI_CTL.SELST field between each serial transfer. The actual behavior of SPI_SEL[n] also depends on the
parameters programmed into the
ty. When SPI_CTL.ASSEL=0, SPI_SEL[n] can either remain active between successive transfers or be inac-
tive. The software must control this activity through manipulation of the
The SPI Transfer Protocol pair of figures illustrates the case when SPI_CTL.ASSEL = 1 and the SPI_SEL[n]
line is inactive between frames. If ASSEL = 0, the SPI_SEL[n] line can remain active between frames; however,
the first bit is only driven when an active transition of SPI_CLK occurs.
Figure 16-2: SPI Transfer Protocol for CPHA=0
Figure 16-3: SPI Transfer Protocol for CPHA=1
Clock Considerations
The SPI_CLK signal is a gated clock that is only active during data transfers, for the time of the transferred word.
In normal mode, the number of active edges is equal to the number of bits to be transmitted or received. In dual-
I/O mode, it is half of the number of bits to be transmitted or received, and in quad-SPI mode it is one-fourth of
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SPI_DLY
register. The SPI hardware logic automatically controls this functionali-
1
2
CLOCK CYCLE
NUMBER
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
SPI_MOSI
MSB
6
*
FROM MASTER
SPI_MISO
MSB
6
FROM SLAVE
SPI_SS
OR SPI_SELn
1
2
CLOCK CYCLE
NUMBER
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
SPI_MOSI
MSB
6
*
FROM MASTER
SPI_MISO
MSB
6
*
FROM SLAVE
SPI_SS
OR SPI_SELn
SPI_SLVSEL
3
4
5
6
7
5
4
3
2
1
5
4
3
2
1
* = UNDEFINED
3
4
5
6
7
5
4
3
2
1
LSB
5
4
3
2
1
* = UNDEFINED
SPI Functional Description
register.
8
LSB
*
LSB
*
8
*
LSB
16–7
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