Analog Devices ADSP-SC58 Series Hardware Reference Manual page 569

Table 13-20: SMPU_SECURECTL Register Fields (Continued)
Bit No.
(Access)
9 RSECDIS
(R/W)
8 RNSEN
(R/W)
3 RLOCK
(R/W)
2 SINTEN
(R/W)
1 SBETYPE
(R/W)
0 SBEDIS
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Secure Read Transaction Disable.
The SMPU_SECURECTL.RSECDIS bit disables secure read transactions.
Non-secure Read Transaction Enable.
The SMPU_SECURECTL.RNSEN bit enables non-secure read transactions.
Secure Region Registers Lock Bit.
When the SMPU_SECURECTL.RLOCK bit is set, the secure region control registers,
SMPU_SECURERCTL[n], are write-protected when the global lock signal is active
from the SPU. When the global lock signal is deasserted, write access is allowed again.
Security Violation Interrupt Enable.
The SMPU_SECURECTL.SINTEN bit enables interrupt generation when a security
violation occurs.
Security Violation Bus Error Type.
The SMPU_SECURECTL.SBETYPE bit controls whether a decode error or a slave
error is returned when a security violation occurs.
Security Violation Bus Error Disable.
The SMPU_SECURECTL.SBEDIS bit controls whether or not a bus error is caused
when a security violation occurs.
ADSP-SC58x SMPU Register Descriptions
Description/Enumeration
0 Enable secure read transactions
1 Disable secure read transactions
0 Disable non-secure read transactions
1 Enable non-secure read transactions
0 Disable write-protection on secure region registers
1 Enable write-protection on secure region registers
0 Disable security settings violation interrupt
1 Enable security settings violation interrupt
0 Return a decode error error which violates the security
settings
1 Return a slave error which violates the security settings
0 Enable bus error
1 Disable bus error
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