Table of Contents
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MSI Features................................................................................................................................................ 26–1
MSI Functional Description ........................................................................................................................ 26–2
ADSP-SC58x MSI Register List ............................................................................................................... 26–2
ADSP-SC58x MSI Interrupt List ............................................................................................................ 26–4
ADSP-SC58x MSI Trigger List................................................................................................................. 26–4
MSI Block Diagram.................................................................................................................................. 26–4
MSI Architectural Concepts ..................................................................................................................... 26–5
Bus Interface Unit (BIU)....................................................................................................................... 26–6
Host Interface Unit (HIU) ................................................................................................................. 26–6
Interrupt Controller Unit .................................................................................................................. 26–6
Register Unit...................................................................................................................................... 26–6
FIFO Controller Unit ........................................................................................................................ 26–7
Power and Pull-up Control and Card Detection Unit ........................................................................ 26–8
Internal Direct Memory Access Controller (IDMAC) .......................................................................... 26–8
DMA Descriptors .............................................................................................................................. 26–8
Initialization..................................................................................................................................... 26–11
Host Bus Burst Access...................................................................................................................... 26–11
Buffer Size Calculations ................................................................................................................... 26–12
Data Transmit/Receive..................................................................................................................... 26–12
Interrupts......................................................................................................................................... 26–13
Finite State Machine (FSM) ............................................................................................................. 26–13
Abort Operation .............................................................................................................................. 26–14
FIFO Overflow and Underflow ........................................................................................................ 26–15
Card Interface Unit ............................................................................................................................. 26–15
Command Path................................................................................................................................ 26–16
Datapath .......................................................................................................................................... 26–18
Auto-Stop......................................................................................................................................... 26–19
Non-Data Transfer Commands that Use Datapath .......................................................................... 26–21
SDIO Interrupt Control .................................................................................................................. 26–21
Clock Control .................................................................................................................................. 26–22
MSI Data Transfer Modes ......................................................................................................................... 26–23
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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