Analog Devices ADSP-SC58 Series Hardware Reference Manual page 930

Figure 19-2: Operation of Timer for Odd Value of PWM_TM
When the timer register value is even, for example 12, then that timer loads +5 at the beginning of the period. The
timer counts from +5 to –6 in the first half, reloads –5 at the midpoint and counts up from –5 to +6 in the second
half. The reload values at the period and mid-period boundaries are different from the previous count. It counts 2 ×
12 half-periods = 24 total counts in the entire period as shown in the Operation of Timer for Even Value of
PWM_TM figure.
Figure 19-3: Operation of Timer for Even Value of PWM_TM
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Count till -(PWM_TMx-1)/2
5
4
3
2
1
0
-1
PWMTMRx
11
Load (PWM_TMx-1)/2
TMRxPHASE
PWM_SYNC
Count till -PWM_TMx -1/2
5
4
3
2
1
0
-1
-2
PWMTMRx
12
Load PWM_TMx/2-1
TMRxPHASE
PWM_SYNC
PWM_TMx = 12
Count till (PWM_TMx-1)/2
3
2
1
0
t
-1
CK
-2 -2
-3 -3
-4 -4
-5 -5
Same as
previous count
11
22
Load (PWM_TMx-1)/2
Load -(PWM_TMx-1)/2
PWM_TMx = 12
Count till -PWM_TMx -1/2
2
1
0
-1
-2
t
CK
-3 -3
-4 -4
-5 -5
-6
Different from
previous count
12
24
Load PWM_TMx/2 - 1
Load -(PWM_TMx/2-1)
5 5
4 4
3
Same as
previous count
2
1
0
6
5 5
4 4
3 Different from 3
previous count
2
1
0
Timer Units
19–9