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Memory-Mapped Mode (SPI2 only)
Table 16-6: Types of Operations (Continued)
SPI Operation
MDMA write
Memory-Mapped Description of Operation
Memory-mapped mode is enabled by setting the SPI_CTL.MMSE bit. When enabled, the SPI (if ready) accepts
the read requests through a dedicated on-chip slave interface. The memory subsystem master drives this dedicated
interface through the SCB fabric.
In a typical scenario, the memory subsystem master issues read requests to the fabric, and the fabric routes these
requests to the slave port of the SPI peripheral. The master describes the read access using a number of parameters
such as starting address, transfer size, and burst type. The SPI responds to this read access request when it is ready
for a new transfer. It loads the opcode, a specified number of address bytes, and an optional mode byte into the
transmit FIFO. The SPI memory state machine begins when both the transmit and receive channels of the SPI are
enabled:
• the transmit transfer initiation bit is set (SPI_TXCTL.TTI=1), and
• the receive initiation bit is cleared (SPI_RXCTL.RTI=0)
The SPI memory read sequence starts with the assertion of SPI_SEL1. If the SPI memory state machine is in the
reset state, it looks for a command. The SPI hardware then sends the specific 8-bit read command (which can be
optionally skipped), followed by the SPI memory read address. After this, a dummy period is inserted, in which a
mode byte is optionally sent and the pins are held or three-stated during the dummy clocking period.
NOTE:
This read header is transmitted over the SPI standard protocol pins (SPI_CLK, SPI_MOSI,
SPI_MISO, SPI_SEL1) or over the extended SPI protocol pins (SPI_CLK, SPI_MOSI, SPI_MISO,
SPI_D2, SPI_D3, SPI_SEL1), based on the SPI_MMRDH.CMDPINS, SPI_MMRDH.ADRPINS,
and SPI_CTL.MIOM bit settings. SPI memory devices usually support communication in MSB-first
mode. In dual mode, the SPI typically uses SPI_MISO as IO1 and SPI_MOSI as IO0. In quad mode,
the SPI typically uses SPI_D3 pin as IO3, SPI_D2 as IO2, SPI_MISO as IO1, and SPI_MOSI as
IO0.
When all I/O data pins are three-stated, the SPI continues clocking the SPI memory device, which drives out the
data bits at the addressed location, until all bytes are received. The SPI hardware reads the data as configured by the
SPI_CTL.MIOM bit setting. Upon reception of the last byte, the SPI typically deasserts SPI_SEL1 to prepare for
the next requested read header.
Application code must ensure that the opcode sent is consistent with multiple I/O programming and that the pa-
rameters specified in the memory-mapped read header register are consistent with flash read access timing.
The SPI Memory-Mapped Register Operations Flow diagram shows how the fields of the
termine the read header while initiating transfers in memory-mapped mode.
16–16
Non-Memory-Mapped Mode
No
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Memory-Mapped Mode
No
SPI_MMRDH
register de-
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