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UART Event Control
UART Event Control
Status flags in the
UART_STAT
sary.
DMA and Interrupt Multiplexing
See the Direct Memory Access (DMA) chapter on for information on DMA multiplexing. Several interrupts and
DMA channels in thr UART can be multiplexed.
To operate in interrupt mode without using DMA channels, set the UART_IMSK.ELSI bit. This config-
NOTE:
uration redirects receive and transmit requests to the status interrupt output. The status interrupt goes di-
rectly to the SEC without going through the DMA controller.
Interrupt Masks
Each UART features a set of interrupt mask registers: UART_IMSK, UART_IMSK_SET, and UART_IMSK_CLR.
The
register supports read/write operations. Writing ones to the
UART_IMSK
interrupts, writing ones to the
bled bits. This way, different interrupt service routines can control transmit, receive, and status interrupt requests
independently and easily.
The UART module uses the
data registers. Unless polling is used as a means of action, the UART_IMSK.ERBFI and UART_IMSK.ETBEI
bits in this register are normally set.
Each UART module has three interrupt outputs. It uses one for transmission, one for reception, and one for report-
ing status events. The UART module routes transmit and receive requests through the DMA controller. The status
request goes directly to the system event controller (SEC).
If the associated DMA channel is enabled, the request functions as a DMA request. If the DMA channel is disabled,
it simply forwards the request to the SEC. A DMA channel must be associated with the UART module to enable
transmit and receive interrupts. Otherwise, transmit and receive requests cannot be forwarded.
NOTE:
To operate in interrupt mode without using DMA channels, set the UART_IMSK.ELSI bit. This config-
uration redirects receive and transmit requests to the status interrupt request output. The status interrupt
goes directly to the SEC without going through the DMA controller.
Interrupt Servicing
Interrupt service routines (ISRs) perform UART writes and reads. Separate interrupt lines are provided for transmit,
receive, and status. The
UART transmit interrupts, set the UART_CTL.EN bit.
The ISRs evaluate the status bits in the
tem event controller for the processor assigns and unmasks interrupts. The ISRs must clear the interrupt latches
explicitly. To reduce interrupt frequency on the receive side in core mode, use the UART_IMSK.ERFCI status
17–18
register are available to signal data reception, parity, and error conditions, if neces-
UART_IMSK_CLR
UART_IMSK
registers to enable requests for system handling of empty or full states of
register group enables the independent interrupts individually. To enable
UART_IMSK
UART_STAT
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register disables them. Reads from either register return the ena-
register to determine the signaling interrupt source. The sys-
register enables
UART_IMSK_SET
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