Table of Contents
Advertisement
ADSP-SC58x L2CTL Register Descriptions
Error Type 1 Register
The
register holds information about the error transaction that has occurred on the bus for the corre-
L2CTL_ET1
sponding L2 bus port 1 (DMA). This register is updated only if the corresponding error status bit
L2CTL_STAT.ERR1 is cleared. After the status bit is set for an error, further errors do not update the
L2CTL_ET1
register until a W1C clears the corresponding status bit. If read and write access errors occur simulta-
neously, the
L2CTL_ET1
(L2CTL_EADDR1).
ID[7:0] (R)
Error ID
RDWR (R)
Read/Write Error
ECCERR (R)
ECC Error
ID[12:8] (R)
Error ID
Figure 9-17: L2CTL_ET1 Register Diagram
Table 9-18: L2CTL_ET1 Register Fields
Bit No.
(Access)
20:8
ID
(R/NW)
4
RDWR
(R/NW)
3
ECCERR
(R/NW)
2
ACCERR
(R/NW)
0
ROMERR
(R/NW)
9–28
captures the write access error, keeping in sync with the error address register
15
14
13
12
11
0
0
0
0
0
31
30
29
28
27
0
0
0
0
0
Bit Name
Error ID.
The L2CTL_ET1.ID bits hold the bus master ID of the access that caused an error.
Read/Write Error.
The L2CTL_ET1.RDWR bit indicates whether a read or write access caused an error.
ECC Error.
If the L2CTL_ET1.ECCERR bit =1, the access had an ECC double-bit error.
Access Error.
If the L2CTL_ET1.ACCERR bit =1, the access went to a restricted bank.
ROM Error.
If the L2CTL_ET1.ROMERR bit =1, a write access went to a ROM area.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
26
25
24
23
22
21
20
19
0
0
0
0
0
0
0
0
Description/Enumeration
0 Read access created error
1 Write access created error
2
1
0
0
0
0
ROMERR (R)
ROM Error
ACCERR (R)
Access Error
18
17
16
0
0
0
Advertisement
Table of Contents
