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ADSP-SC58x CGU Register Descriptions
PLL Control Register
The
register contains bits that enable and disable the PLL as well as control its function.
CGU_PLLCTL
PLLEN (R/W)
PLL Enable
PLLDIS (R/W)
PLL Disable
LOCK (R/W)
Lock
Figure 3-9: CGU_PLLCTL Register Diagram
Table 3-15: CGU_PLLCTL Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
3
PLLEN
(R/W)
2
PLLDIS
(R/W)
1
PLLBPCL
(R/W)
3–26
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Lock.
Setting (=1) the CGU_PLLCTL.LOCK bit locks access to the
PLL Enable.
Setting (=1) the CGU_PLLCTL.PLLEN bit enables the PLL.
PLL Disable.
Setting (=1) the CGU_PLLCTL.PLLDIS bit disables the PLL.
PLL Bypass Clear.
Setting (=1) the CGU_PLLCTL.PLLBPCL bit takes the PLL out of bypass mode.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 Unlock register
1 Lock register
0 No action
1 Enable PLL
0 No action
1 Disable PLL
0 No action
1 Exit bypass mode
1
0
0
0
PLLBPST (R/W)
PLL Bypass Set
PLLBPCL (R/W)
PLL Bypass Clear
17
16
0
0
CGU_PLLCTL
register.
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