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End of Interrupt Register (ICCEOIR)
A processor writes to the
service routine for the specified interrupt.
VALUE[31:16] (R/W)
End of Interrupt
Figure 7-51: GICCPU_EOI Register Diagram
Table 7-53: GICCPU_EOI Register Fields
Bit No.
(Access)
31:0
VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
GICCPU_EOI
register to inform the CPU interface that it has completed its interrupt
15
0
VALUE[15:0] (R/W)
End of Interrupt
31
0
Bit Name
End of Interrupt.
The GICCPU_EOI.VALUE bit field indicates to the CPU interface that it has com-
pleted its interrupt service routine for the specified interrupt.
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x GICCPU Register Descriptions
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
7–83
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