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Shared Peripheral Interrupt Processor Targets Register
The
GICDST_SPI_TRGT[n]
GIC.
Figure 7-47: GICDST_SPI_TRGT[n] Register Diagram
Table 7-48: GICDST_SPI_TRGT[n] Register Fields
Bit No.
(Access)
7:0
VALUE
(R/W)
ADSP-SC58x GICCPU Register Descriptions
GIC CPU Port (GICCPU) contains the following registers.
Table 7-49: ADSP-SC58x GICCPU Register List
Name
GICCPU_BIN_PT_ALIAS
GICCPU_BIN_PT
GICCPU_CTL
GICCPU_EOI
GICCPU_PND_HI
GICCPU_INT_ACK
GICCPU_PRIO_MSK
GICCPU_RUN_PRIO
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register provides an 8-bit CPU targets field for each interrupt supported by the
VALUE (R/W)
Shared Peripheral Interrupt Processor
Targets
Bit Name
Shared Peripheral Interrupt Processor Targets.
The GICDST_SPI_TRGT[n].VALUE bit field stores the list of processors that the
interrupt is sent to if it is asserted.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Description/Enumeration
Description
Aliased Binary Point Register (ICCABPR)
Binary Point Register (ICCBPR)
CPU Interface Control Register (ICCICR)
End of Interrupt Register (ICCEOIR)
Highest Pending Interrupt Register (ICCHPIR)
Interrupt Acknowledge Register (ICCIAR)
Priority Mask Register (ICCIPMR)
Running Priority Register (ICCRPR)
ADSP-SC58x GICDST Register Descriptions
0
0
7–79
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