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Control Register
The
register configures the EPPI for operating mode, control signal polarities, and data width of the
EPPI_CTL
port.
POLS (R/W)
Frame Sync Polarity
POLC (R/W)
Clock Polarity
SIGNEXT (R/W)
Sign Extension
IFSGEN (R/W)
Internal Frame Sync Generation
ICLKGEN (R/W)
Internal Clock Generation
BLANKGEN (R/W)
king Generation (ITU Output Mode)
CLKGATEN (R/W)
Clock Gating Enable
MUXSEL (R/W)
MUX Select
DMAFINEN (R/W)
DMA Finish Enable
DMACFG (R/W)
One or Two DMA Channels Mode
RGBFMTEN (R/W)
RGB Formatting Enable
SPLTWRD (R/W)
Split Word
SUBSPLTODD (R/W)
Sub-Split Odd Samples
Figure 18-15: EPPI_CTL Register Diagram
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
ADSP-SC58x EPPI Register Descriptions
EN (R/W)
PPI Enable
DIR (R/W)
PPI Direction
XFRTYPE (R/W)
Transfer Type ( Operating Mode)
FSCFG (R/W)
Frame Sync Configuration
FLDSEL (R/W)
Field Select/Trigger
ITUTYPE (R/W)
ITU Interlace or Progressive
DLEN (R/W)
Data Length
DMIRR (R/W)
Data Mirroring
SKIPEN (R/W)
Skip Enable
SKIPEO (R/W)
Skip Even or Odd
PACKEN (R/W)
Pack/Unpack Enable
SWAPEN (R/W)
Swap Enable
SPLTEO (R/W)
Split Even and Odd Data Samples
18–55
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