Analog Devices ADSP-SC58 Series Hardware Reference Manual page 404

ADSP-SC58x L2CTL Register Descriptions
Table 9-21: L2CTL_STAT Register Fields (Continued)
Bit No.
(Access)
12 ECCERR4
(R/W1C)
11 ECCERR3
(R/W1C)
10 ECCERR2
(R/W1C)
9 ECCERR1
(R/W1C)
8 ECCERR0
(R/W1C)
4 RFRS
(R/NW)
9–32
Bit Name
ECC Error Bank 4.
The L2CTL_STAT.ECCERR4 bit indicates that an ECC double-bit error occurred
inside L2 bank 4.
ECC Error Bank 3.
The L2CTL_STAT.ECCERR3 bit indicates that an ECC double-bit error occurred
inside L2 bank 3.
ECC Error Bank 2.
The L2CTL_STAT.ECCERR2 bit indicates that an ECC double-bit error occurred
inside L2 bank 2.
ECC Error Bank 1.
The L2CTL_STAT.ECCERR1 bit indicates that an ECC double-bit error occurred
inside L2 bank 1.
ECC Error Bank 0.
The L2CTL_STAT.ECCERR0 bit indicates that an ECC double-bit error occurred
inside L2 bank 0.
Refresh Register Status.
The L2CTL_STAT.RFRS bit indicates whether a refresh request is pending (in prog-
ress) or that there are no pending requests.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No Status
1 ECC Double Bit Error
0 No Status
1 ECC Double Bit Error
0 No Status
1 ECC Double Bit Error
0 No Status
1 ECC Double Bit Error
0 No Status
1 ECC Double Bit Error
0 No Pending Requests
1 Request Pending (Refresh in Progress)