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write error occurs if an attempt is made to write a lock RCU register. The address error occurs if a read-only register
is written to or if an attempt is made to a reserved address within the RCU MMR address range.
Resetting the ARM Core through Another Core or System Mas-
ter
The RCU allows reset of a given core n using another core or system master. Core 0 can be individually reset by
software, either setting any of CR0 bit in the
that all the system transactions to or from it have completed. Although a core n reset can be triggered by core n
itself, it is recommended that another core or system master trigger it. Core n can be reset to restore its functionality
when it cannot execute software.
The following steps show the suggested programming sequence to reset core n only.
1. Clear the RCU_CRSTAT.CR[n] bit.
2. Disable interrupts to core n
3. Set the RCU_SIDIS.SI[n] bit to disable the interfaces for core n, to stop DMA accesses to its L1, to stop
accesses to memory for core n, and stop accesses to MMRs.
4. Test the RCU_SISTAT.SI[n] bit to detect when accesses to core n have been disabled and all the pending
transactions have completed.
5. Set the RCU_CRCTL.CR[n] bit to reset core n.
6. Poll the RCU_CRSTAT.CR[n] bit until core n is in reset.
7. Once the core is in reset, clear the RCU_SIDIS.SI[n] bit to reenable the core interfaces.
8. Clear the RCU_CRCTL.CR[n] bit to take core n out of reset.
9. Poll the RCU_CRSTAT.CR[n] bit until core n is out of reset.
Resetting a SHARC+ Core Through Another Core
Resetting a SHARC+ core involves a software handshake between the Master core which issues a reset to the
SHARC+ core. The handshake is done using a core interrupt along with message passing through a variable in
shared L2 memory RAM. Each SHARC+ core needs two bits for handshaking.
• Core Reset Request bit (CRR). This bit is set by the master core to indicate to the SHARC+ core that a core
reset needs to be done. If the CRR bit is set the SHARC+ core should disable all interrupts, stop all system and
memory accesses and enter the IDLE state.
• IDLE acknowledgement (IDLE). Once the SHARC+ core is ready for reset, it sets this bit before entering the
IDLE state to inform the master core that it is ready for reset.
Two bits are needed for SHARC0 core and two bits are needed for SHARC1 core. These bits are:
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Resetting the ARM Core through Another Core or System Master
RCU_CRCTL
register. Cores that reset themselves cannot guarantee
6–5
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