Analog Devices ADSP-SC58 Series Hardware Reference Manual page 436

ADSP-SC58x DMC Register Descriptions
Table 10-13: DMC_CTL Register Fields (Continued)
Bit No.
(Access)
3 SRREQ
(R/W)
2 INIT
(R0/W)
1 LPDDR
(R/W)
0 DDR3EN
(R/W)
10–30
Bit Name
Self-Refresh Request.
The DMC_CTL.SRREQ bit enables self-refresh mode. When the DMC is in self-re-
fresh mode, any data accesses cause the DMC to generate a bus error. The DRAM re-
mains in self-refresh mode as along as this bit is 1.
Initialize DRAM Start.
The DMC_CTL.INIT bit starts the power up DRAM initialization sequence and
DLL calibration sequence. Note that this bit always reads as 0.
Low Power DDR Mode.
The DMC_CTL.LPDDR bit selects whether the DMC operates in low power DDR
mode or DDR2 mode.
DDR3 Mode.
The DMC_CTL.DDR3EN bit selects whether the DMC operates in DDR3 mode or
DDR2 mode.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Disable Self-Refresh
1 Enable Self-Refresh
0 No Effect
1 Start DRAM Initialization
0 DDR2 mode
1 LPDDR mode
0 Enable DDR2 mode
1 Enable DDR3 mode