Analog Devices ADSP-SC58 Series Hardware Reference Manual page 849

EPPI Architectural Concepts
Figure 18-6: Transmit Data Path
Reset Operation
On a hardware reset, the entire EPPI is reset. All MMRs return to their default values. EPPI interrupt and DMA
requests become inactive and internally generated EPPI_CLK and frame syncs are aborted.
In software, write 0 to the EPPI_CTL.EN bit to reset and reconfigure the EPPI. When disabled in this manner,
only the EPPI_STAT
nally generated clock and frame syncs are aborted.
Frame Sync Polarity and Sampling Edge
The EPPI_CTL.POLS and EPPI_CTL.POLC bits provide a mechanism to select the active level of the frame
syncs and the sampling or driving edge of the EPPI clock, respectively. This functionality allows the EPPI to connect
to data sources and receivers with a wide array of control signal polarities. Often, the remote data source or receiver
also offer configurable signal polarities. In these cases, the EPPI_CTL.POLS and EPPI_CTL.POLC bits add
flexibility.
Table 18-6: Frame Sync Polarity Selections and Frame Sync Pin States
Bit Setting
POLS = b#00
POLS = b#01
POLS = b#10
POLS = b#11
18–10
SCB BUS
0
register is cleared to its reset value. Interrupts and DMA requests become inactive and inter-
Frame Sync 2
Active high
Active high
Active low
Active low
DMA
DMA
CH0
CH1
SCLK0 domain
EPPI clock domain
YFIFO CFIFO
UNPACK UNPACK
DATA DATA
EPPI_UNPACKDP
CLIP
CLIP_DATA_OUT
1
CLIP_EN
BLANKGEN_DATA
0 1
BLANKGEN_EN
dataout_x2f
EPPI_DATA_OUT
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Frame Sync 1
Active high
Active low
Active high
Active low