Analog Devices ADSP-SC58 Series Hardware Reference Manual page 14

Data Calibration Data 0 Register .......................................................................................................... 10–33
Data Calibration Data 1 Register .......................................................................................................... 10–34
Efficiency Control Register .................................................................................................................... 10–35
Shadow EMR1 DDR2 Register ............................................................................................................. 10–39
Shadow EMR2 Register (DDR2)/Shadow EMR Register (LPDDR) ..................................................... 10–41
Shadow MR Register (DDR2/LPDDR), Shadow MR0 Register (DDR3) ............................................. 10–43
Shadow MR1 Register (DDR3) ............................................................................................................. 10–46
Shadow MR2 Register (DDR3) ............................................................................................................. 10–49
Mask (Mode Register Shadow) Register ................................................................................................. 10–51
Priority ID Register 1 ............................................................................................................................ 10–53
Priority ID Register 2 ............................................................................................................................ 10–54
Priority ID Mask Register 1 ................................................................................................................... 10–55
Priority ID Mask Register 2 ................................................................................................................... 10–56
DMC Read Data Buffer ID Register 1 .................................................................................................. 10–57
DMC Read Data Buffer ID Register 2 .................................................................................................. 10–58
DMC Read Data Buffer Mask Register 1 .............................................................................................. 10–59
DMC Read Data Buffer Mask Register 2 .............................................................................................. 10–60
Status Register ....................................................................................................................................... 10–61
Timing 0 Register .................................................................................................................................. 10–64
Timing 1 Register .................................................................................................................................. 10–66
Timing 2 Register .................................................................................................................................. 10–67
ADSP-SC58x DMC Register Descriptions ............................................................................................... 10–68
Calibration PAD Control 0 Register ...................................................................................................... 10–69
Calibration PAD Control 2 Register ...................................................................................................... 10–70
PHY Control 0 Register ........................................................................................................................ 10–71
PHY Control 1 Register ........................................................................................................................ 10–72
PHY Control 2 Register ........................................................................................................................ 10–73
PHY Control 3 Register ........................................................................................................................ 10–74
PHY Control 4 Register ........................................................................................................................ 10–75
xiv ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference